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Added 41 mins ago
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Senior/Principal Custom IC Layout Engineer
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- $140,000 to $190,000 CAD / year
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Inpho

Senior/Principal Custom IC Layout Engineer

Ottawa, ON, Canada
Kanata, ON, Canada

$140,000 to $190,000 CAD / year · Full-time

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Job details

Pay: $140,000 to $190,000 CAD / year
Job type: Full-time
Apply by: Apr 3, 2027
Experience: 7+ years of CMOS/BiCMOS/SiGe process technology expertise, with direct experience in high-speed or RF variants.
Posting language: English
Posted: Oct 5, 2026

Original job description

About Inpho

Inpho is a fast-growing scale-up, focused on developing cutting-edge optoelectronic solutions for next-generation communications, and photonic systems. Our multidisciplinary team is pushing the boundaries of innovation in integrated photonics and semiconductor packaging.

Inpho’s new class of electro-photonic chips is poised to revolutionize and disrupt the optical interconnect market. Utilizing this new class of chips enables existing optical interconnect systems to be built at much lower cost; new architectures to be deployed that provide significantly higher price/performance; and a whole new generation of higher speed interconnect to be built that to date have been impossible.

About the Role

We are seeking a Senior/Principal Custom IC Layout Engineer who will contribute to Inpho’s innovative products, designing and implementing industry leading laser/EAM drivers and TIAs in both SiGe and InP. This includes fully integrated electronic-photonic ICs that are unique in the industry.

Key Responsibilities

Own and execute complex custom IC layout blocks from schematic through tapeout.
Translate circuit schematics and design specifications into optimized physical layouts.
Perform floorplanning, placement, routing, shielding, matching, and layout optimization.
Apply advanced layout techniques including common-centroid structures, interdigitation, symmetry, dummy devices, guard rings, substrate isolation, and sensitive-node shielding.
Work closely with circuit designers to understand circuit intent and optimize layout for performance, area, noise, matching, and reliability.
Perform and debug DRC, LVS, ERC, antenna, density, and other physical verification checks.
Analyze and minimize parasitic resistance, capacitance, coupling, and substrate effects.
Support parasitic extraction and post-layout simulation and help resolve layout-dependent performance issues.
Coordinate with circuit design, verification, CAD, process, and foundry teams as required.
Identify opportunities to improve layout quality, productivity, automation, and design methodology.
Mentor other engineers and contribute to the technical growth of the layout team.

Qualifications

Bachelor's degree in Electrical or Computer Engineering preferred; advanced degree a plus.
7+ years of CMOS/BiCMOS/SiGe process technology expertise, with direct experience in high-speed or RF variants.
Proficiency in Cadence Virtuoso or Keysight ADS layout (at least one required; both strongly preferred at this level), plus Calibre, Assura, and PVS for verification and extraction sign-off.
Demonstrated top-level floorplanning experience, from architectural block placement through final signoff, on multi-block or multi-die designs
Hands-on ESD layout design experience.
Proven layout experience on high-speed circuits: differential/matched pairs, transmission-line structures, EM-aware routing, and isolation/shielding for high-frequency blocks.
Experience leading layout efforts across multiple, geographically distributed design teams/sites.
Direct, working-level experience interfacing with foundry and assembly/packaging houses (design kit qualification, DRC/LVS/PDK sign-off, package co-design, bond-pad/RDL considerations).
Strong communication skills and the ability to work independently and as part of a fast-paced engineering team.

Preferred Experience

Prior exposure to III-V compound semiconductor processes (InP, GaAs) is a strong plus and accelerates ramp into InP HBT layout.
Track record mentoring or reviewing work of layout engineers.
Comfortable serving as the layout point-of-contact across cross-functional design, foundry, and packaging teams.
Startup or high-growth environment experience.

Why Join Inpho?

Be part of a mission-driven startup shaping the future of photonics
Competitive salary, full health benefits and equity packages, flexible work environment, and career growth opportunities.

Come work with a dynamic, high-talent team to build and commercialize the highest-performance photonics chips in the world!

Additional Information

This posting is for a newly created position.

The expected compensation range for this position is CAD$140,000 - $190,000 annually. Actual compensation offered for this position will be determined based on a variety of factors, including the candidate’s skills, level, experience, qualifications, and overall fit for the role.

Inpho may use Artificial Intelligence (AI) to support aspects of the recruitment process, including candidate screening and assessment. All final hiring decisions are made by Inpho’s Hiring Team.

Inpho is an equal opportunity employer committed to fostering an inclusive, diverse, and respectful workplace. We provide equal employment opportunities without discrimination based on race, colour, religion, sex, gender identity or expression, sexual orientation, national origin, age, disability, veteran status, or any other characteristic protected by applicable law.

If you require accommodation during the recruitment process, please contact Inpho Human Resources at hr@inpho.io

We thank all candidates for their interest in Inpho. Only those candidates selected for an interview will be contacted.

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More about this job

Responsibilities

Own complex custom IC layout blocks from schematic through tapeout, including floorplanning, placement, routing, optimization, and physical verification. Collaborate with circuit, verification, CAD, foundry, and packaging teams to improve performance and reliability, resolve post-layout issues, and mentor layout engineers.

Requirements

A bachelor's degree in Electrical or Computer Engineering is preferred, along with at least seven years of CMOS, BiCMOS, or SiGe experience and proficiency in Cadence Virtuoso or Keysight ADS. Candidates should have top-level floorplanning, ESD and high-speed/RF layout, physical verification, foundry and packaging interface, and distributed-team leadership experience; III-V process experience is a plus.

Skills

Custom IC Layout
Cadence Virtuoso
Keysight ADS
Calibre
Assura
PVS
Floorplanning
Physical Verification
DRC/LVS/ERC
High-Speed Circuit Layout
RF Layout
ESD Layout
Parasitic Extraction
SiGe
InP
Team Leadership

Benefits

Health Benefits
Equity Packages
Flexible Work Environment
Career Growth Opportunities

Visa sponsorship

Not detected in the job text

Keywords

Custom IC Layout
Integrated Photonics
Electro-Photonic Chips
Laser Drivers
EAM Drivers
TIAs
SiGe
InP
CMOS
BiCMOS
Cadence Virtuoso
Keysight ADS
Calibre
Assura
PVS
Floorplanning
Placement And Routing
Common-Centroid Structures
Interdigitation
Guard Rings
Substrate Isolation
DRC
LVS
ERC
ESD Layout
Parasitic Extraction
Post-Layout Simulation
Transmission-Line Structures
EM-Aware Routing
Package Co-Design

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