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Insight Global

IC Design Verification Engineer

Ottawa, ON, Canada

Pay: $110,600 to $152,000 CAD / year
Job type: Full-time
Apply by: Nov 1, 2026
Experience: 5+ years of experience in IP & System on Chip (SoC) products.
Posting language: English
Posted: Oct 2, 2026

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Original job description

Job Description

Join a highly experienced R&D team dedicated to developing Intellectual Property (IP) for advanced microcontrollers and microprocessors. This team focuses on creating a networking switch and network controller IP core (NETC) that supports the latest TSN standards, forming the networking foundation for the latest microcontrollers, processors, and switches. The IP developed by this team underpins a product portfolio generating billions of USD in annual revenue. The chips you help develop are likely found in the car you drive, the smart devices in your home, and the factories producing the goods you use.

Part of AI and Chip Engineering (ACE), developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products.

Job Description

We are seeking a highly motivated Design Verification Engineer with a relentless drive to excel and make a significant impact. Our team offers innovative thinking, engineering expertise, and sustained market leadership in embedded processing. By joining us, you will work with the advanced platforms that we deliver to major players in the automotive, industrial, edge, and telecommunication markets, featuring multiple processing cores and high-performance networking accelerators integrated on the same silicon chip.

Responsibilities:

Architect, design, implement, and verify breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial, and edge computing markets.
Responsible for the architecture, design, and implementation of UVM Verification of hardware IP & System on Chip (SoC) products.
Perform thorough trade-off analysis on performance and complexity.
Work closely with IP architecture, design, and verification teams on planning and execution to ensure the IP is delivered on time and with the highest quality.
Produce quality documentation for all phases of the project, including detailed IP functional and implementation specifications.
Build the directed and random verification tests
Debug test failures to determine the root cause; work with architect and design engineers to resolve defects and correct issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Proactively drive continuous improvement in design and verification methodology.

Job Qualifications:

5+ years of experience in IP & System on Chip (SoC) products.
Thorough knowledge and expertise in System Verilog and UVM Verification.
Strong understanding of IP & SoC development methodology and proficiency in verification tools.
Strong Experience in EDA tools and scripting (Python, TCL, Perl, Makefile, Shell) used to build tools and flows for verification environments
Strong Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with revision control systems like Git
Familiarity with hardware and software implementation trade-offs.
Focus on quality results with proven problem-solving abilities.
Algorithm development experience.
Strong interpersonal, communication, and documentation skills.
Dynamic team player.
Bachelor's degree in Computer Science, Engineering, or a related field.

Highly Desirable Skills:

Familiarity with Formal and Functional Safety Verification.
Knowledge of state-of-the-art networking technologies, including TCP/IP protocols.
Experience with data products such as routers, bridges, and switches.
Security/cryptography experience.

Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to roles in our Canada locations and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $110,600 to $152,000 CAD.

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More about this job

Responsibilities

Architect, implement, and verify Ethernet and networking IP and SoC products, including UVM verification environments, tests, and coverage plans. Collaborate with architecture, design, and verification teams to debug defects, deliver high-quality IP on schedule, document specifications, and improve verification methods.

Requirements

Requires at least five years of experience with IP and SoC products, strong SystemVerilog and UVM expertise, and experience building verification infrastructure and executing the full verification cycle. A bachelor's degree in Computer Science, Engineering, or a related field is required, along with proficiency in EDA tools, scripting, revision control, problem-solving, and communication; formal or functional safety verification and networking knowledge are desirable.

Skills

SystemVerilog
UVM Verification
Design Verification
IP and SoC Development
Verification Infrastructure
Directed and Random Testing
Functional and Code Coverage
EDA Tools
Python
TCL
Perl
Makefile
Shell Scripting
Git
Algorithm Development
Ethernet and Networking IP

Visa sponsorship

Not detected in the job text

Keywords

SystemVerilog
UVM
Design Verification
Intellectual Property
System on Chip
SoC
Ethernet
Networking IP
TSN Standards
EDA Tools
Python
TCL
Perl
Makefile
Shell Scripting
Git
Directed Testing
Random Testing
Functional Coverage
Code Coverage
Verification Infrastructure
Formal Verification
Functional Safety Verification
TCP/IP
Routers
Bridges
Switches
Security
Cryptography
Automotive

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