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ITI

Senior Hardware Design Engineer

Ottawa, ON, Canada
Greater Ottawa Metropolitan Area, Canada

Pay: $100,000 to $150,000 CAD / year
Job type: Full-time
Apply by: Oct 22, 2026
Experience: 7+ years of FPGA, ASIC, RTL, or verification experience
Posting language: English
Posted: Sep 22, 2026

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Original job description

Multiple Openings | Ottawa Preferred | Hybrid Flexibility

We're hiring for a few Senior Engineering positions supporting advanced FPGA, ASIC, and chiplet development programs focused on high-performance computing, AI, networking, and high-speed connectivity applications.

We're looking for engineers with 7+ years of experience in FPGA design, ASIC RTL development, or verification who enjoy solving complex technical challenges and working closely with architecture, firmware, verification, and implementation teams. These opportunities involve technologies such as SystemVerilog, UVM, PCIe, Ethernet, UCIe, SerDes, and other high-speed interfaces.

Current Openings

Senior FPGA Design Engineer

FPGA design using SystemVerilog from specification through timing closure
RTL development, CDC analysis, synthesis setup, and timing constraints
Opportunity to grow into a design lead role

Senior RTL Design Engineer

Front-end RTL development for advanced chiplet and high-speed connectivity solutions
SystemVerilog and Verilog development, protocol and PHY IP integration
CDC/RDC analysis, synthesis, and front-end sign-off activities
Experience with PCIe, Ethernet, UCIe, or other high-speed interfaces is highly desirable

Senior Verification Engineer

SystemVerilog and UVM-based verification of complex ASIC and chiplet designs
Verification planning, VIP integration, coverage closure, and sign-off
Experience with SoC, high-speed interface, or die-to-die verification is an asset

Desired Experience

7+ years of FPGA, ASIC, RTL, or verification experience
Strong SystemVerilog and/or Verilog expertise
ASIC, FPGA, or SoC development experience
High-speed interfaces such as PCIe, Ethernet, SerDes, or UCIe
CDC/RDC methodologies, synthesis, timing analysis, and timing closure
Python, Tcl, or similar scripting languages
ASIC tape-out experience is an asset

Work Arrangement

Ottawa preferred
Hybrid arrangements may be available depending on the role and project
Candidates must be eligible to work in Canada

If your background aligns with FPGA design, RTL development, or verification engineering and you're interested in learning more, we'd be happy to connect.

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More about this job

Responsibilities

The role involves developing advanced FPGA, ASIC, and chiplet solutions for high-performance computing, AI, and networking applications. Engineers will work across the full development lifecycle, including RTL design, verification, synthesis, and timing closure.

Requirements

Candidates must have 7+ years of experience in FPGA, ASIC, or verification engineering with strong expertise in SystemVerilog or Verilog. Proficiency in high-speed interfaces and standard industry methodologies like CDC/RDC analysis is required.

Skills

FPGA Design
ASIC RTL Development
Verification
SystemVerilog
Verilog
PCIe
Ethernet
UCIe
SerDes
CDC Analysis
Synthesis
Timing Closure
Python
Tcl
SoC
PHY IP Integration

Visa sponsorship

Not detected in the job text

Keywords

FPGA
ASIC
Chiplet
RTL
SystemVerilog
Verilog
PCIe
Ethernet
UCIe
SerDes
CDC
RDC
Synthesis
Timing Closure
Verification
SoC
Python
Tcl
High-performance computing
AI
Networking
PHY IP
Tape-out
Firmware
Architecture

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