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Added 7 mins ago
DC
Environmental Student
Dillon Consulting Limited
Fredericton, NB
- Other
Working towards an Environmental/Civil Engineering degree/diploma, a degree in environmental sciences, or a related environmental field
Added 21 mins ago
J
Senior Director, Engineering
Jobgether
Canada
- Full-time
We are seeking a senior engineering leader to drive the architecture, development, and delivery of advanced embedded memory IP solutions for semiconductor applications. In this high-impact…
Added 52 mins ago
AI
Embedded Software Architect
Aversan Inc.
Montreal, QC
- $135,000 to $155,000 CAD / year
- Full-time
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- Full-time
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Field Technical Lead - Security Systems
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Jobgether

Senior Director, Engineering

Canada

Full-time

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Job details

Job type: Full-time
Posting language: English
Posted: Nov 8, 2026

Original job description

This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is looking for a Senior Director, Engineering based in Canada.

We are seeking a senior engineering leader to drive the architecture, development, and delivery of advanced embedded memory IP solutions for semiconductor applications. In this high-impact role, you will lead multidisciplinary memory design teams and shape the technical roadmap across multiple process technologies. You will oversee the development of SRAM, ROM, register files, and dual-port RAM compilers, ensuring competitive performance, power, area, and yield. Combining deep circuit-design expertise with strategic leadership, you will also serve as a senior technical partner to customers throughout presales, integration, and silicon qualification. You will collaborate with engineering, product, sales, and foundry teams to translate complex requirements into production-ready solutions. This is an opportunity to influence next-generation semiconductor technologies while developing engineering talent and strengthening customer partnerships.

Accountabilities

Lead the architecture, circuit design, and physical implementation of embedded memory compilers, including SRAM, ROM, single- and dual-port register files, and dual-port RAM.
Define key memory design elements, including bitcell selection, peripheral architecture, decoders, sense amplifiers, write drivers, I/O, self-timing, redundancy, repair strategies, and assist circuits.
Drive optimization of minimum operating voltage (Vmin), leakage, performance, area, and yield across process, voltage, and temperature (PVT) corners, process variation, and aging conditions.
Own the technical roadmap for the memory portfolio, including new compiler variants, process nodes, feature enhancements, and design methodology improvements.
Establish design, verification, and signoff methodologies, leading design and layout reviews, SPICE/FastSPICE characterization, statistical and Monte Carlo analysis, BIST/repair, DFT, and physical verification.
Lead silicon validation programs, including test chip development, testing, characterization, and reporting.
Lead, mentor, and develop a team of memory design engineers across circuit design, layout, characterization, and compiler automation.
Define team objectives, conduct technical reviews, establish career development paths, and promote engineering rigor and continuous improvement.
Allocate engineering resources across product roadmaps, customer commitments, and silicon programs while managing schedules, dependencies, and technical risks.
Act as the senior technical lead in presales engagements, presenting the memory portfolio, qualifying opportunities, and shaping competitive technical proposals.
Translate customer SoC requirements, including frequency, voltage, density, power, port configuration, and operating modes, into compiler specifications and PPA commitments.
Partner with sales, field application engineering, and product management teams on RFQs, technical evaluations, and competitive benchmarking.
Lead technical workshops and detailed design discussions with customer architects and engineering teams, responding to technical questionnaires and audit-style reviews.
Own PPA analysis across the memory portfolio, evaluating performance, active and leakage power, area, and yield at both instance and SoC levels.
Maintain competitive benchmarks against foundry and third-party memory IP, identify performance gaps, and prioritize improvements.
Conduct sensitivity and trade-off analyses to guide architecture decisions, including bitcell selection, mux ratios, banking, assist circuits, and operating voltage ranges.
Develop customer-facing technical materials, including datasheets, application notes, and technical white papers.
Serve as the primary technical contact for strategic customers throughout evaluation, integration, tapeout, and silicon validation.
Lead integration debugging, technical reviews, silicon correlation discussions, and root-cause analysis of customer-reported issues.
Coordinate issue resolution across design, characterization, CAD, and product teams, and represent the organization in foundry partner meetings and industry conferences when required.

Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
10+ years of embedded memory design experience, including demonstrated production tapeouts of SRAM and at least two additional memory types among ROM, single-port register files, dual-port register files, and dual-port RAM.
Deep expertise in bitcell-level circuit design, memory peripheral circuits, self-timed paths, sense amplifier design, and assist circuit techniques.
Hands-on experience across multiple semiconductor process nodes, including FinFET and/or advanced sub-7nm technologies.
Strong command of SPICE simulation, statistical and Monte Carlo analysis, Vmin and yield modeling, and reliability analysis covering BTI, HCI, and electromigration.
Working knowledge of memory compiler architecture and automation, including instance generation and the production of views such as Liberty (.lib), LEF, GDS, Verilog, and CDL.
Practical experience with DFT and scan tools such as Tessent or FastScan, power integrity signoff tools such as RedHawk or equivalents, and physical verification flows including DRC, LVS, and parasitic extraction.
Familiarity with RTL/Verilog modeling of memory compilers, test chip definition, silicon correlation, and SDK or automation development for compiler view generation.
Proven engineering leadership experience, either through direct management or a senior technical leadership role overseeing a team of at least six memory designers.
Demonstrated success in customer-facing technical roles, including presales engagements, PPA negotiations, and integration support.
Excellent written and verbal communication skills, with the ability to present complex technical concepts to engineers, architects, and executive stakeholders.
Proficiency in scripting languages such as Python, TCL, or Perl, and experience working in Linux-based design environments.
Experience using AI tools such as Claude, OpenAI, or Gemini to support technical and engineering workflows.
Experience presenting at industry conferences or technical venues such as ISSCC, VLSI Symposium, or custom integrated circuits conferences, or contributing to memory IP standards.
Direct experience working with foundry partners on PDKs, bitcell qualification, and reference flow alignment.

Preferred Qualifications

Experience leading memory compiler programs at a semiconductor IP vendor, foundry, or large semiconductor company.
Background in low-power memory design for mobile, IoT, automotive, or AI/ML accelerator applications.
Experience with multi-port memory architectures beyond two ports, such as three-port or four-port register files, and specialty memories including TCAM and multi-bank arrays.

Benefits

Opportunity to lead advanced embedded memory IP development and influence semiconductor design across multiple technology nodes.
Potential eligibility for equity, bonuses, commission, or other forms of additional compensation, depending on the position offered.
Comprehensive medical, financial, and other employee benefits.
Compensation determined by role, level, geographic location, relevant experience, technical skills, education, and other job-related factors.

How Jobgether Works

We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team.

We appreciate your interest and wish you the best!

Why Apply Through Jobgether?

Data Privacy Notice: By submitting your application, you acknowledge that Jobgether will process your personal data to evaluate your candidacy and share relevant information with the hiring employer. This processing is based on legitimate interest and pre-contractual measures under applicable data protection laws (including GDPR). You may exercise your rights (access, rectification, erasure, objection) at any time.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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More about this job

Responsibilities

Lead the architecture, design, implementation, optimization, and validation of embedded memory IP and compilers across multiple process technologies, while owning the memory portfolio’s technical roadmap. Manage and develop a multidisciplinary engineering team, and serve as the senior technical partner to customers and foundry teams through presales, integration, tapeout, and silicon qualification.

Requirements

Requires a bachelor's, master's, or doctoral degree in electrical engineering, computer engineering, or a related discipline, plus 10 or more years of embedded memory design experience and production tapeouts of SRAM and at least two other memory types. Candidates should bring deep circuit-design and semiconductor-process expertise, experience leading a team of at least six memory designers, customer-facing technical leadership, and proficiency with relevant simulation, verification, automation, and Linux-based design tools.

Skills

Embedded Memory Design
SRAM Circuit Design
Memory Compiler Architecture
Bitcell Design
SPICE Simulation
PPA Optimization
Semiconductor Process Technologies
Memory Characterization
Silicon Validation
DFT and Scan
Physical Verification
Verilog
Python
TCL
Engineering Leadership
Customer Technical Support

Benefits

Equity
Bonuses
Commission
Medical Benefits
Financial Benefits

Visa sponsorship

Not detected in the job text

Keywords

Embedded Memory IP
SRAM
ROM
Register Files
Dual-Port RAM
Memory Compilers
FinFET
Sub-7nm Technologies
SPICE
FastSPICE
Monte Carlo Analysis
Vmin Modeling
Yield Modeling
BTI
HCI
Electromigration
Liberty
LEF
GDS
Verilog
CDL
Tessent
FastScan
RedHawk
DRC
LVS
Parasitic Extraction
Python
TCL
Perl

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