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  • Added

    Senior ASIC RTL Design Engineer, AI Networking IP

    Advanced Micro Devices, Inc

    Ottawa, ON

    • Full-time

    Work with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support

  • Added

    Senior ASIC RTL Design Engineer, AI Networking IP

    AMD

    Ottawa, ON · Kanata, ON

    • $128,000 to $192,000 USD / year
    • Full-time

    Work with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support

  • Added

    Senior Engineer - Design

    Microchip Technology Inc.

    Burnaby, British Columbia · Canada - Burnaby

    • Full-time

    Design, code, and integrate synthesizable RTL in SystemVerilog/Verilog and VHDL, ensuring designs meet functional, timing, area, and power targets.

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