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Sr. Manager - RTL Design Manager
Advanced Micro Devices, Inc
Collaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.
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Sr. Manager - RTL Design Manager
AMD
Collaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.
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FY27 Intern - Silicon Engineering Internship - Canada (16 months)
Qualcomm
At Qualcomm Canada, our Applications Engineering - Post Silicon Team is looking for hardware and firmware engineering interested in working on the leading edge SERDES technology. The intern…
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FY27 Intern - IP Applications Engineering Internship - Canada (16 months)
Qualcomm
…hands-on experience with customer support, IP integration, and silicon bring-up activities while developing your technical skills in SerDes technologies, validation, and automation. You…
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FY27 Intern - Low-Power AI, Audio, and Sensors Subsystem Engineering Internship - ASIC Firmware / Embedded - Canada (12 or 16 months)
Qualcomm
For LPAI ASIC Silicon Validation and Emulation Intern, Key Responsibilities/Exposures:
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Digital Design Manager
Astera Labs
…signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure. You will partner with design, verification, physical design, packaging,…
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Technical Program Manager - Software, Firmware, Emulation, and Validation (Ottawa)
Qualcomm
Qualcomm is seeking a Technical Program Manager to lead planning, development, execution, and delivery of software, emulation, and silicon validation for Networking Products within the…
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Technical Program Manager - Software, Firmware, Emulation, and Validation (Vancouver)
Qualcomm
Qualcomm is seeking a Technical Program Manager to lead planning, development, execution, and delivery of software, emulation, and silicon validation for Networking Products within the…
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Sr. Manager, Physical Design Engineering, Annapurna Labs
Amazon Web Services (AWS)
Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and…
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3rd Party IP Technical Lead
AMD
Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture --> integration --> post-silicon validation --> production.
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3rd Party IP Technical Lead
Advanced Micro Devices, Inc
Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture --> integration --> post-silicon validation --> production.
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Sr. Principal Program Manager, ASIC Design
Astera Labs
Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.
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