Design Verification Intern
- Toronto, ON, Canada
- CA-ON - Ontario - Toronto, Canada
Full-time
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Job details
- Job type
- Full-time
- Posting language
- English
- Posted
Original job description
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
This is an existing vacancy.
Your Team, Your Impact
Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.What You Can Expect
Design Verification Intern is responsible for the design verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He or she will be responsible for block and /or chip level verification.
The responsibilities include but not limited to.
- Design verification for various type of D2D IPs and SerDes IPs ranging from 10Gbps to 448Gbps data-rates for different applications.
- Use and improve UVM DV environment
- Improve the design methodology and flow.
- Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
- Provide the support to the product teams, for both pre and post silicon
What We're Looking For
Approved Intern for 2027 Calendar Year
Bachelor/Master students in Electrical/Computer Engineering related programs
Good personal communication skills and team working spirit.
Hardworking and motivated to be part of a highly competent design team.
Highly desirable skills:
- Understand ASIC verification flows and methodologies
- Verilog, SystemVerilog, UVM
- UNIX Shell scripting (Csh, Bash)
- Experience with VIPs
- Formal verification
- PCIe, UCIe protocol knowledge
- Low power design
- MATLAB and C/C++ based system simulation and evaluation
- DSP function hardware implementation knowledge
- Strong Perl and Python scripting
Expected Base Pay Range (CAD)
32 - 43, $ per hour.


Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.
More about this job
Responsibilities
The intern will be responsible for the design verification and evaluation of digital circuits in high-speed data communication ICs. This includes developing verification plans, setting up test environments, and collaborating with cross-functional teams to deliver competitive SerDes IP solutions.
Requirements
Candidates must be Bachelor or Master students in Electrical or Computer Engineering for the 2027 calendar year. Strong technical skills in ASIC verification, SystemVerilog, UVM, and scripting languages are highly desirable.
Skills
- Design verification
- SystemVerilog
- UVM
- Verilog
- UNIX
- Shell scripting
- Csh
- Bash
- Perl
- Python
- PCIe
- UCIe
- MATLAB
- C/C++
- DSP
- ASIC verification
Benefits
- Competitive compensation
- Collaborative work environment
- Professional development opportunities
Visa sponsorship
Not detected in the job text
Categories
- Technology
- Engineering
- Software
Keywords
- Design Verification
- Semiconductor
- SerDes
- PHY
- Analog Mixed-Signal
- ASIC
- UVM
- SystemVerilog
- Verilog
- UNIX
- Shell Scripting
- PCIe
- UCIe
- MATLAB
- C++
- C
- DSP
- Perl
- Python
- Data Infrastructure
- IC Design
- Low Power Design
- Formal Verification
- Hardware Implementation
- Firmware
- Analog Design
- Digital Design
- Data Communication
- Engineering
- Technology