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Mirafra Technologies

CAD Engineer (Conformal LEC)

Canada

Full-time

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Job details

Job type: Full-time
Posting language: English
Posted: Nov 3, 2026

Original job description

Job Description:

A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development

Key Responsibilities

Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows.

ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications.

Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages.

Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell.

Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors.

AI Enablement : Enable AI enabled tools and methodologies

Core Requirements

Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality.

Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience

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More about this job

Responsibilities

Develop and maintain end-to-end logic equivalence checking sign-off methodologies across RTL-to-GDS and gate-to-gate flows, including support for safe engineering change orders. Debug equivalence failures and optimize verification tools and automation for runtime, capacity, and scalability, while enabling AI-based methodologies and collaborating with EDA vendors.

Requirements

Candidates should be proficient with industry-standard logic equivalence tools, including Cadence Conformal and Synopsys Formality, and have dedicated hardware or EDA experience. A bachelor's or master's degree in Electrical Engineering, Computer Science, or a related field is specified.

Skills

Logic Equivalence Checking
Formal Verification
RTL-to-GDS Flows
Gate-to-Gate Verification
Engineering Change Orders
Debugging
Root Cause Analysis
Tcl
Python
Perl
Shell Scripting
Tool Optimization
Cadence Conformal
Synopsys Formality
AI-Enabled Verification

Visa sponsorship

Not detected in the job text

Keywords

Logic Equivalence Checking
LEC
Formal Verification
RTL
Synthesized Netlists
Physical Design
System-on-Chip
RTL-to-GDS
Gate-to-Gate Flows
Sign-Off Methodologies
Engineering Change Orders
ECO
Non-Equivalence Debugging
Root Cause Analysis
Tcl
Python
Perl
Shell
Cadence Conformal
Synopsys Formality
EDA Tools
Tool Optimization
Runtime Optimization
Scalability
AI-Enabled Tools
Semiconductor Manufacturing

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