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Added 10 days ago
S
Senior Design Engineer, Microelectronics and Advanced Packaging
Sanmina
Ottawa, ON
- $110,000 to $160,000 CAD / year
- Full-time
We are seeking a Senior Design Engineer, Microelectronics and Advanced Packaging to join our team to support and lead both technology and product development programs, from initial…
Added 10 days ago
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Senior Microelectronics Process Engineer
Sanmina
Ottawa, ON
- $145,000 to $165,000 CAD / year
- Full-time
Minimum 8+ years of direct, hands-on experience in microelectronics packaging and process engineering.
Added 24 days ago
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Staff Process Engineer
Nokia
Canada
- Full-time
As a Staff Process Engineer, you will be at the forefront of innovation, driving the development of assembly processes for state-of-the-art electro-optical modules. Your expertise in SMT,…
Added 1 month ago
VE
Microelectronics Ultrapure Water (UPW) Senior Process Engineer
Veolia Environnement SA
Oakville, ON
- Full-time
Microelectronics UPW Process Engineers lead the process design of ultrapure water treatment solutions for the
Added 1 month ago
S
Mechanical Design Engineer
Sanmina
Ottawa, ON
- Full-time
…from design concept, through prototype design and testing, process development, assembly and test innovation, to volume manufacturing. We are extremely proud to partner with our customers…
Added 1 month ago
S
Mechanical Design and Analysis Engineer
Sanmina
Ottawa, ON
- Full-time
…from design concept, through prototype design and testing, process development, assembly and test innovation, to volume manufacturing. We are extremely proud to partner with our customers…
Added 1 month ago
S
Principal Hardware Designer
Sanmina
Ottawa, ON
- Full-time
Interface with mechanical engineers, optical engineers, microelectronics engineer, firmware engineers, process engineers and test engineers.
Added 1 month ago
Test Engineer Senior
Acuity Inc.
Brossard, QC
Understanding of microelectronics and basic programming.
Added 22 days ago
HT
Engineer - 6G RF Packaging
Huawei Technologies Canada Co., Ltd.
Ottawa, ON
- Full-time
Huawei Canada has an immediate permanent opening for an Engineer.
Added 23 days ago
MT
Physical Design Engineer
Mirafra Technologies
ON · Ontario, Canada
- Full-time
We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving…
Added 5 months ago
T
Circuit Analyst
TechInsights
Ottawa, Ontario
- Full-time
…includes detailed circuit analysis, imagery, semiconductor process flows, device teardowns, illustrations, costing and pricing information, forecasts, market analysis, and expert…

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Mirafra Technologies

Physical Design Engineer

ON, Canada
Ontario, Canada, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Oct 9, 2026
Posting language: English
Posted: Sep 9, 2026

Original job description

Role Overview

We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving timing closure across complex, sub-nanometer process nodes while leveraging next-generation development tools. You will play a key role in developing, optimizing, and automating physical design workflows using Tcl and Python, incorporating AI-assisted development tools like GitHub Copilot to accelerate script delivery and engineering efficiency.

Key Responsibilities

Static Timing Analysis (STA): Execute timing signoff, constraint validation, multi-corner multi-mode (MCMM) analysis, and timing closure across all phases of physical implementation.
Flow Automation & Scripting: Write, maintain, and enhance robust automated scripts using Tcl and Python to streamline EDA tool flows (place & route, synthesis, signoff).
AI-Assisted Development: Utilize Copilot-assisted development tools to rapidly build, refactor, and test flow automation scripts, optimizing operational productivity.
Timing & Power Optimization: Analyze setup/hold violations, crosstalk, IR drop, and clock path issues, collaborating closely with RTL and synthesis teams to achieve optimal PPA (Power, Performance, Area).
Process Improvement: Standardize scripting frameworks, build continuous regression tests for physical design tools, and document automated methodologies for the broader team.

Qualifications

Required Skills & Experience:

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
Core STA Expertise: In-depth understanding of Static Timing Analysis principles, timing constraints (SDC), clock jitter, skew, cross-talk noise, and signoff methodologies using industry tools (e.g., Synopsys PrimeTime or Cadence Tempus).
Scripting Proficiency: Strong hands-on coding ability in Tcl (for EDA tool integration) and Python (for data processing and workflow automation).
Modern Development Tooling: Direct experience or strong familiarity with Copilot-assisted coding/script development tools (or LLM-driven coding tools) to write, debug, and optimize scripts efficiently.
VLSI Fundamentals: Sound understanding of digital CMOS logic, place and route (PnR) flow fundamentals, and physical verification concepts.

Preferred Qualifications:

Experience with automated tool API integrations (e.g., Synopsys ICC2/Fusion Compiler, Cadence Innovus APIs).
Experience implementing CI/CD pipelines or automated regression frameworks for hardware design flows.
Background in Git or modern version control systems for managing Tcl/Python script repositories.

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More about this job

Responsibilities

The role involves driving timing closure and executing signoff across sub-nanometer process nodes. It also focuses on automating physical design workflows using Tcl, Python, and AI-assisted development tools.

Requirements

Candidates must have a degree in Electrical or Computer Engineering and deep expertise in Static Timing Analysis and scripting. Proficiency with modern LLM-driven coding tools and VLSI fundamentals is required.

Skills

Static Timing Analysis
Tcl
Python
Timing Closure
Physical Design
Synopsys PrimeTime
Cadence Tempus
SDC
PPA Optimization
VLSI
CMOS Logic
Place and Route
GitHub Copilot
Physical Verification
CI/CD Pipelines
Git

Visa sponsorship

Not detected in the job text

Keywords

Physical Design
Static Timing Analysis
STA
Tcl
Python
GitHub Copilot
Synopsys PrimeTime
Cadence Tempus
MCMM
SDC
PPA
VLSI
CMOS
Place and Route
PnR
Physical Verification
IR Drop
Crosstalk
Synopsys ICC2
Fusion Compiler
Cadence Innovus
CI/CD
Git
Semiconductor Manufacturing
Sub-nanometer Process Nodes

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