ASIC Physical Design Engineer

The Opportunity:

Movellus is pioneering on-chip power management for AI-scale silicon, with IP deployed across millions of units in complex SoC architectures. Our technologies deliver real-time PDN telemetry, Ldi/dt detection, mitigation, DFS, and DVFS. We tackle multi-dimensional engineering challenges at the nexus of digital, analog, signal processing, and control systems.

At Movellus, we promise fun, not easy - offering an environment for engineers passionate about leading power efficiency in the AI era.

We’re seeking a motivated and skilled ASIC Physical Design Engineer to join our growing engineering team. This role offers an exciting opportunity to contribute to the physical realization of high-performance digital integrated circuits, owning key stages of our RTL-to-GDSII implementation flow. The ideal candidate will possess a solid understanding of the ASIC implementation flow, with practical experience in RTL design (SystemVerilog), synthesis, place and route (PNR), static timing analysis (STA), and power/EMIR analysis. You will work collaboratively with the team on challenging projects, playing a key role in bringing innovative digital designs to silicon.

Responsibilities:

• Own and drive key stages of the RTL-to-GDSII flow - including synthesis, place and route (PNR), static timing analysis (STA), power/EMIR (IR-drop, electromigration) analysis, DFT insertion, and physical verification (DRC/LVS) - to help deliver tapeout-ready GDSII.
• Perform static timing analysis (STA) at various stages of the design flow and work closely with RTL designers to resolve timing violations and implement necessary design changes.
• Perform power analysis and optimization - including IR-drop, electromigration (EM), and power grid/rail sign-off (EMIR) - throughout the implementation flow.
• Generate and validate timing constraints (SDC) and support the RTL synthesis process, including constraint generation and optimization.
• Analyze synthesis, PNR, STA, and power/EMIR reports to identify and resolve potential issues, and help refine the CAD flow accordingly.
• Document implementation strategies, analysis results, and best practices.
• Collaborate effectively with cross-functional teams, including architects, RTL engineers, verification engineers and post-slicon verification engineers.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering or a related field.
• Canadian Permanent Residency (PR) or Citizenship required.
• Minimum of 4 years of relevant experience in ASIC implementation.
• Solid knowledge of the complete RTL-to-GDSII implementation flow, including synthesis, place and route, static timing analysis, power/EMIR analysis, DFT, and physical verification (LVS/DRC).
• Hands-on experience with industry-standard EDA/CAD tools for synthesis, PNR, STA, and power/EMIR sign-off (e.g., Synopsys Design Compiler/ICC2/Custom Compiler, Cadence Genus/Innovus/Virtuoso, PrimeTime, Ansys RedHawk-SC).
• Familiarity with timing constraint generation (SDC).
• Understanding of power analysis and optimization techniques, including IR-drop and electromigration (EM) checks, in the context of implementation.
• Exposure to DFT (scan insertion/ATPG) and physical verification (DRC/LVS) flows is a plus.
• Knowledge of scripting languages such as Python or TCL for CAD flow automation is a plus.
• Strong understanding of digital logic design principles and RTL development using SystemVerilog.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.

What we Offer :

• A dedicated ambitious team with a vast range of talent across software and hardware.
• Become part of a growing startup in the chip-making hardware industry.
• Hybrid working model for our office in Markham - Canada.
• Competitive total compensation package. All regular employees are eligible for company stock in the form of stock options.
• Comprehensive medical, dental, and vision coverage.
• Retirement savings through a defined contribution pension or savings plan.
• Flexible PTO/Paid Time Off policy in addition to statutory holidays.