Senior ASIC Verification Engineer (35885)
- Ottawa, ON, Canada
- Kanata, ON, Canada
Full-time
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Job details
- Job type
- Full-time
- Apply by
- Experience
- 8+ years of relevant experience in ASIC or SoC verification.
- Posting language
- English
- Posted
Original job description
Senior ASIC Verification Engineer
Role Overview
Work as an independent contributor in the development and verification of advanced SoCs based on the latest ASIC and FPGA technologies. The role involves developing robust verification environments, creating test strategies, and collaborating with cross-functional engineering teams to deliver high-quality silicon and hardware solutions.
Key Responsibilities
Role Overview
Work as an independent contributor in the development and verification of advanced SoCs based on the latest ASIC and FPGA technologies. The role involves developing robust verification environments, creating test strategies, and collaborating with cross-functional engineering teams to deliver high-quality silicon and hardware solutions.
Key Responsibilities
- Develop and verify complex SoCs and digital ASIC designs using SystemVerilog and UVM.
- Develop protocol and traffic generators, checkers, and self-checking verification environments.
- Develop and execute comprehensive test plans based on functional requirements and applicable industry standards.
- Define, develop, and execute verification tests for complex digital ASICs at the block and sub-chip levels.
- Collaborate with hardware, software, system engineers, suppliers, and other technical teams to resolve complex technical issues.
- Work closely with subject matter experts across different engineering disciplines to develop competitive and reliable solutions.
- Support hardware and software bring-up, integration, debugging, and issue resolution.
- Apply functional coverage, code coverage, assertions, and formal verification techniques to improve verification quality.
- Contribute independently to assigned projects or provide technical leadership to a verification team when required.
- Help evaluate and implement evolving verification methodologies, tools, and best practices.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline; Master's degree is preferred.
- 8+ years of relevant experience in ASIC or SoC verification.
- Strong experience developing and implementing verification test plans for complex ASICs at the block or sub-chip level.
- Advanced proficiency in SystemVerilog and scripting languages such as Python.
- Strong knowledge and hands-on experience with the UVM methodology.
- Experience with SystemVerilog Assertions (SVA) and functional coverage.
- Experience with code coverage and formal verification tools.
- Understanding of modern and evolving ASIC/SoC verification methodologies.
- Strong analytical and problem-solving skills.
- Excellent communication and collaboration skills.
- Ability to work effectively within geographically distributed, cross-functional engineering teams.
- Experience with DSP and/or FEC is considered an asset.
More about this job
Responsibilities
Develop and verify complex SoCs and digital ASICs using SystemVerilog and UVM, including verification environments, test plans, generators, checkers, coverage, assertions, and formal techniques. Collaborate across engineering teams to resolve technical issues, support integration and bring-up, and contribute independently or provide technical leadership.
Requirements
Requires a bachelor's degree in a relevant engineering or computer science discipline and 8 or more years of ASIC or SoC verification experience; a master's degree is preferred. Candidates should have advanced SystemVerilog and Python skills, strong UVM experience, and hands-on knowledge of assertions, coverage, and formal verification, along with analytical and collaboration skills.
Skills
- SystemVerilog
- UVM
- ASIC Verification
- SoC Verification
- Python
- SystemVerilog Assertions
- Functional Coverage
- Code Coverage
- Formal Verification
- Verification Test Planning
- Protocol and Traffic Generators
- Digital Design Verification
- Hardware and Software Bring-Up
- Debugging
- DSP
- FEC
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- ASIC
- SoC
- FPGA
- SystemVerilog
- UVM
- Python
- Digital Design
- Verification Environment
- Verification Test Plans
- Functional Requirements
- Industry Standards
- Protocol Generators
- Traffic Generators
- Checkers
- Self-Checking Verification
- SystemVerilog Assertions
- Functional Coverage
- Code Coverage
- Formal Verification
- Hardware Bring-Up
- Software Bring-Up
- Integration
- Debugging
- Verification Methodologies
- DSP
- FEC
- Cross-Functional Engineering