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Added 27 days ago
Turbine and Generator, Mechanical Engineer (Engineer V)
Énergie NB Power
Fredericton, NB
$52.23 to $65.32 CAD / hour
Full-time
As part of the Mactaquac Life Achievement Project (MLAP), the Turbine and Generator, Mechanical Engineer V will be responsible for overseeing and executing technical and project-related…
Added 16 days ago
Engineer V (Hydroelectric Electrical Engineer)
Énergie NB Power
Fredericton, NB
$52.23 to $65.32 CAD / hour
Full-time
As part of the Mactaquac Life Achievement Project (MLAP), the Turbine and Generator, Hydroelectric Electrical Engineer (Engineer V) will be responsible for overseeing and executing…
Added 1 month ago
[Fastwater Staffing] Satellite System V&V Engineer | Montreal, Canada (Full Relocation Package)
HIKINEX
Canada
Full-time
The Satellite-Level Verification and Validation (V&V) Engineer focuses on the highest tier of spacecraft integration, ensuring the fully assembled satellite meets all mission, launch…
Added 2 days ago
Verification & Validation (V&V) Test Engineer
Akkodis
Toronto, ON
Contract
Position: Verification & Validation (V&V) Test Engineer
Added 1 month ago
[Fastwater Staffing] Payload System V&V Engineer | Montreal, Canada (Full Relocation Package)
HIKINEX
Canada
Full-time
We are is looking for qualified Payload System Verification and Validation Engineers to join our advanced satellite payload development team. This role focuses on system-level engineering…
Added 8 days ago
Senior V&V Test Engineer - Autonomous Vehicles
CS GROUP
Montreal, QC
Full-time
We are looking for a Senior V&V Test Engineer to support the validation of autonomous vehicle systems and vehicle-level interfaces.
Added 8 days ago
Senior V&V Test Engineer - Autonomous Vehicles
CS GROUP - Canada
Montreal, QC
Full-time
We are looking for a Senior V&V Test Engineer to support the validation of autonomous vehicle systems and vehicle-level interfaces.
Added 8 days ago
Senior V&V Test Engineer - Autonomous Vehicles
Sopra Steria
Montreal, QC
Full-time
We are looking for a Senior V&V Test Engineer to support the validation of autonomous vehicle systems and vehicle-level interfaces.
Added 27 days ago
Civil Engineering Construction Lead (Engineer V)
Énergie NB Power
Fredericton, NB
$52.23 to $65.32 CAD / hour
Full-time
As part of the Mactaquac Life Achievement Project, the Engineer V (Civil Engineering Construction Lead) is responsible for enhancing the effectiveness of project delivery through strong…
Added 1 month ago
Senior OpenShift Virtualization (OCP-V) Engineer
OPTICCA CONSULTING INC.
Quebec, QC
Full-time
Opticca Consulting is seeking a highly experienced Senior OpenShift Virtualization (OCP-V) Engineer to design, implement, migrate, secure, and operate enterprise virtual-machine platforms…
Added 3 days ago
Verification Engineer V
TekWissen ®
Markham, ON
$104.57 USD / hour
Contract
…semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing Client verification solutions for complex Display IP…
Added 2 months ago
EIS QA Engineer II
V-Soft Consulting Group, Inc.
Mississauga, ON
Contract
V-Soft Consulting is currently hiring for an EIS QA Engineer II for our premier client in Mississauga, Ontario.
Added 4 days ago
Design Verification Engineer
Net2Source (N2S)
Markham, ON
$92 to $102 CAD / hour
Contract
Join Display IP team that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing…
Added 1 month ago
Satellite System Verification & Validation Engineer for Fastwater Staffing
HIKINEX
Montreal, QC
Contract
The Satellite-Level Verification and Validation (V&V) Engineer focuses on the highest tier of spacecraft integration, ensuring the fully assembled satellite meets all mission, launch…
Added 1 month ago
Civil Engineers
ADVANTEC Consulting Engineers, Inc.
Engineer, BC
Full-time
The ideal candidate will have over 5 years' experience in roadway engineering and public works engineering, preferably with Caltrans project delivery experience from PID to PS&E phases. You…
Added 1 month ago
Design engineers
ADVANTEC Consulting Engineers, Inc.
Engineer, BC
Full-time
The ideal candidate will have over 3 years’ experience and work on multi-modal engineering projects involving highway design, freeway interchange improvements, ITS, and other disciplines.…
Added 1 month ago
[Fastwater Staffing] Platform Systems Verification & Validation Engineer | Montreal, Canada (Full Relocation Package)
HIKINEX
Canada
Full-time
The Platform Systems Verification and Validation (V&V) Engineer focuses on the satellite bus, ensuring the core infrastructure subsystems are fully verified and ready to support the payload.
Added 1 month ago
Platform System Verification & Validation Engineer for Fastwater Staffing and Recruiting
HIKINEX
Montreal, QC
Contract
The Platform Systems Verification and Validation (V&V) Engineer focuses on the satellite bus, ensuring the core infrastructure subsystems are fully verified and ready to support the payload.
Added 8 days ago
RF System Verification Engineer
Actalent
Sainte-Anne-de-Bellevue, QC
Contract
We are seeking Payload System Verification and Validation Engineers to support advanced satellite payload development programs. The team is expanding significantly, with approximately 30…
Added 16 days ago
Avionics & Communication – IPT Head
Pentangle Tech Services | P5 Group
Montréal-Est, QC
Full-time
Education: Bachelor’s/Master’s in Aerospace, Avionics, Electrical Engineering, or Electronics & Communication
Added 6 days ago
Avionics & Communication - IPT Head
Katalyst CRO
Montreal, QC
Contract
Reports to: Program Manager / Chief Engineer.
Added 16 days ago
IPT Head - Avionics & Communication
Pentangle Tech Services | P5 Group
Montreal, QC
Full-time
Leads: Avionics IPT team (System, Design, V&V, Certification engineers)
Added 15 days ago
Power Engineer | Maintenance Worker
Interior Health Authority
Nelson, BC
Full-time
We are looking for an experienced Power Engineer 5 / Maintenance Worker V to join our dedicated and supportive team at the Kootenay Lake Regional Hospital in Nelson, BC.
Added 17 days ago
Field Applications Engineer, IP Product
Tenstorrent
Vancouver, BC · Toronto, ON
Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end…
Added 4 days ago
Flight Control Systems (FCS)- IPT Head
Katalyst CRO
Montreal, QC
Contract
Bachelor's or Master's degree in Aerospace Engineering, Control Systems Engineering, Mechanical Engineering, or Electrical Engineering.

Net2Source (N2S)

Design Verification Engineer

Markham, ON, Canada

Pay: $92 to $102 CAD / hour
Job type: Contract
Apply by: Oct 15, 2026
Posting language: English
Posted: Sep 15, 2026

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Original job description

Title: Verification Engineer V

Location: Markham, ON (Hybrid - 3 days per week onsite )

Duration: 8 Months (Possible extension)

Pay Range: $92 to $102 per hour on T4

The Role

Join Display IP team that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs. You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market.

The ideal candidate is passionate about verification methodologies, possesses strong expertise in SystemVerilog/UVM-based verification environments, and has hands-on experience with formal verification, functional coverage planning, and coverage-driven verification. This individual will thrive in a collaborative environment and enjoy solving complex technical challenges across all phases of product development.

Key Responsibilities

Define and execute comprehensive verification strategies for complex IP and subsystem designs.

Develop verification plans based on architecture and design specifications.

Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.

Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.

Develop functional coverage plans and coverage models, and drive coverage closure.

Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.

Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.

Develop and maintain assertion-based verification (SVA) infrastructure and verification content.

Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.

Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.

Analyze verification metrics and recommend improvements to verification quality and efficiency.

Contribute to verification methodology development, automation, and continuous process improvement.

Preferred Experience

8-10+ years of experience in ASIC, IP, or SoC verification.

Strong expertise in SystemVerilog, UVM, and constrained-random verification methodologies.

Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.

Hands-on experience with formal verification methodologies and industry-standard formal verification tools.

Strong understanding of assertion-based verification (SVA) and formal property development.

Experience creating reusable verification environments, verification IP, and verification infrastructure.

Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.

Experience with simulation, regression management, coverage analysis, and debug tools.

Experience working through multiple successful silicon product cycles.

Strong communication and collaboration skills.

Preferred Technical Skills

Experience in one or more of the following areas is considered an asset:

Display IP and display subsystem verification

Formal verification and assertion-based verification (ABV)

Functional coverage architecture and coverage closure methodologies

Graphics, multimedia, and video processing pipelines

Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI

High-speed interfaces and protocols

Memory subsystem verification

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More about this job

Responsibilities

The role involves defining and executing comprehensive verification strategies for complex Display IP and SoC designs. Key tasks include developing UVM testbenches, creating functional coverage plans, and applying formal verification methodologies to ensure first-pass silicon success.

Requirements

Candidates should have 8-10+ years of experience in ASIC or SoC verification with strong expertise in SystemVerilog and UVM. Proficiency in formal verification, assertion-based verification (SVA), and experience with display protocols is highly preferred.

Skills

SystemVerilog
UVM
Formal Verification
Functional Coverage
SVA
ASIC Verification
SoC Verification
Constrained-Random Verification
DisplayPort
HDMI
MIPI
eDP
Digital Design
Computer Architecture
Regression Management
Root-Cause Analysis

Visa sponsorship

Not detected in the job text

Keywords

SystemVerilog
UVM
Formal Verification
SVA
ASIC
SoC
Display IP
Functional Coverage
Constrained-Random
DisplayPort
HDMI
MIPI
eDP
Hardware Verification
Digital Design
Computer Architecture
Verification IP
Regression Management
Silicon Product Cycle
Multimedia Pipelines
Video Processing
High-Speed Interfaces
Memory Subsystem
Property Checking
Assertion-Based Verification

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