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Added 2 mins ago
Robotics Engineer
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Deploy and test your solution on different platforms
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Co-op ASIC Digital Verification Engineer
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Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to…
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NUVACORE

CPU Architect Verification Engineer

Markham, ON, Canada

Pay: $140,000 to $250,000 USD / year
Job type: Full-time
Apply by: Oct 28, 2026
Experience: 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Posting language: English
Posted: Sep 30, 2026

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Original job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification - checking the CPU's behavior and architectural state against the architecture specification and a golden reference model - building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.
Environment Setup: Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.
Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Requirements - Must To Have

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU architecture and micro-architecture - the instruction set, architectural state, exceptions, and privilege model - with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
Hands-on functional verification: test plans, testbenches, checkers, and coverage.
Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.

Requirements - Nice To Have

Architectural / instruction-set verification against a golden reference model.
Random instruction sequence (RIS) stimulus generation.
Exceptions, interrupts, privilege levels, and virtualization.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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More about this job

Responsibilities

Plan and execute architectural verification of CPU behavior and state against specifications and a golden reference model, including building verification environments, generating assembly and random instruction tests, and closing functional coverage. Collaborate with architecture and RTL teams to debug mismatches, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Requirements

Requires a degree in Electrical or Computer Engineering, Computer Science, or equivalent practical experience, plus 15+ years of design-verification experience for Principal level or 4+ years for Senior Engineer level. Candidates need CPU architecture knowledge, hands-on functional verification experience, proficiency in C/C++, Rust, and/or SystemVerilog plus scripting, and experience writing and debugging assembly tests.

Skills

CPU Architecture
Design Verification
Architectural Verification
SystemVerilog
C/C++
Rust
Python
Assembly Language
Functional Verification
Test Planning
Testbench Development
Functional Coverage
Random Instruction Sequences
Golden Reference Model Co-Simulation
Assertions
Formal Verification

Visa sponsorship

Not detected in the job text

Keywords

CPU
CPU Architecture
Microarchitecture
Design Verification
Architectural Verification
Instruction Set Architecture
x86
ARM
RISC-V
SystemVerilog
C/C++
Rust
Python
Perl
Assembly Language
Golden Reference Model
Co-Simulation
Random Instruction Sequences
Constrained-Random Verification
Functional Coverage
Coverage-Driven Closure
Exceptions
Interrupts
Privilege Levels
Virtualization
Assertions
Formal Verification
Emulation
FPGA
Silicon Bring-Up

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