Jobs in Toronto, ON and nearby

Jobs within 25 km of Toronto, ON, Canada. Nearby towns and cities are included. Distances are straight-line, not driving distances.

73,780 listings · 9,572 employers Counted Oct 24, 2026. How we count

About these jobs

Employers hiring include Shoppers Drug Mart (1,213 listings), Loblaw Companies Limited (1,028 listings), Scotiabank (757 listings).

Common roles: Software engineer, Project manager, Retail sales associate.

12,119 of these listings include employer-provided pay. Open a job to see its currency and pay period.

Advertised starting pay
Pay period	Median starting pay	Listings
CAD / year	85,000.00	6,701
CAD / hour	25.00	4,321
USD / year	110,000.00	477
USD / hour	26.48	234
CAD / month	4,500.00	19
CAD / week	2,868.82	18

Employer-listed minimums from at least 10 listings per currency and pay period. These are advertised starting amounts, not employee salaries. Jobs without a minimum and unusual amounts are excluded.

Workplace classifications: 0% remote, 29% hybrid, 71% on-site, 0% not specified. Hybrid and on-site classifications may be inferred from descriptions. Check the original ad.

Based on the dated count above. Listings can change. How we count

Jobs in Toronto, ON and nearby

Within 25 km

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NUVACORE

CPU Architect Verification Engineer

Markham, ON, Canada

$140,000 - $250,000 a year · Full-time

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Applications open in a new tab.

Job details

Pay: $140,000 - $250,000 a year
Job type: Full-time
Experience: 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Posting language: English
Posted: Sep 8, 2026

Original job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification - checking the CPU's behavior and architectural state against the architecture specification and a golden reference model - building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.
Environment Setup: Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.
Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS - MUST TO HAVE

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU architecture and micro-architecture - the instruction set, architectural state, exceptions, and privilege model - with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
Hands-on functional verification: test plans, testbenches, checkers, and coverage.
Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.

REQUIREMENTS - NICE TO HAVE

Architectural / instruction-set verification against a golden reference model.
Random instruction sequence (RIS) stimulus generation.
Exceptions, interrupts, privilege levels, and virtualization.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

\n\n

$140,000 - $250,000 a year

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More about this job

Responsibilities

You will drive the verification strategy and test plans to ensure architectural correctness of the CPU against specifications and golden reference models. This involves building robust verification environments, generating stimulus, and collaborating with RTL and architecture teams to root-cause bugs.

Requirements

Candidates must have a degree in Electrical/Computer Engineering or Computer Science with extensive experience in CPU design verification. Proficiency in C/C++/Rust, SystemVerilog, and assembly language is required, along with deep knowledge of modern ISA architectures.

Skills

CPU Architecture
Design Verification
RTL Design
C
C++
Rust
SystemVerilog
Python
Perl
Assembly
Instruction Set Architecture
Functional Verification
Formal Verification
Emulation
FPGA
Silicon Bring-up

Visa sponsorship

Not detected in the job text

Keywords

CPU
Verification Engineer
RTL
Architecture
Micro-architecture
ISA
x86
ARM
RISC-V
Testbench
Checkers
Coverage
RIS
Exceptions
Interrupts
Privilege levels
Virtualization
Constrained-random
Assertions
Formal verification
Waveforms
Trace
Nuvacore

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