Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at
multiple levels - from Senior Engineer to Principal level - to help prove that the Nuvacore CPU is architecturally correct. As part of the
design verification (DV) team, you will help drive architectural verification - checking the CPU's behavior and architectural state against the architecture specification and a golden reference model - building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.
THE ROLE
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Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.
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Environment Setup: Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.
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Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
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Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
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Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.
REQUIREMENTS - MUST TO HAVE
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Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
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15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
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Strong knowledge of CPU architecture and micro-architecture - the instruction set, architectural state, exceptions, and privilege model - with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
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Hands-on functional verification: test plans, testbenches, checkers, and coverage.
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Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
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Experience writing and debugging tests in assembly for CPU verification.
REQUIREMENTS - NICE TO HAVE
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Architectural / instruction-set verification against a golden reference model.
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Random instruction sequence (RIS) stimulus generation.
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Exceptions, interrupts, privilege levels, and virtualization.
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Constrained-random verification and coverage-driven closure.
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Assertions and formal verification.
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Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
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$140,000 - $250,000 a year
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