Closed listing
CPU DFT Engineer
- Markham, ON, Canada
$140,000 to $250,000 USD / year · Full-time
This opening has closed.
The original listing is kept below for reference.
Job details
- Pay
- $140,000 to $250,000 USD / year
- Job type
- Full-time
- Closing date
- Experience
- BS or MS with 7 years experience in DFT or DFT verification
- Posting language
- English
- Posted
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Search current openingsOriginal job description
Archived listing. The details below describe a past opening.
- Multiple Levels
- Austin and Santa Clara
THE ROLE
As a CPU DFT Engineer, you will participate in the following areas:
- Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
- Develop scan and BIST insertion flows, implement DFT registers in design blocks
- Completing DFT architecture specifications
- Review and integrate third party IPs into DFT architecture
- Define verification plans for DFT features
- Review DFT coverage for scan and MBIST
- Verification of DFT features in RTL and gates, and power aware simulations
- Generate test content for silicon bringup, and support silicon bringup activities including yield analysis
- BS or MS with 7 years experience in DFT or DFT verification
- Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
- For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
- For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
- Strong understanding of JTAG, IEEE 1500 and IEEE 1687
- Experience with Verilog RTL and gate level netlists, including running and debugging simulations
- Strong communication skills and ability to work with cross functional teams
- Using DFT features to support system debug
- Leveraging AI tools to accelerate DFT work flows
- Porting test content and supporting silicon bringup on ATE platforms
- Experience in perl, python, or TCL
More about this job
Responsibilities
Define and implement area- and power-efficient DFT architecture, develop scan and BIST insertion flows, and integrate third-party IP while collaborating with design, STA, and physical design teams. Verify DFT features and coverage, generate silicon test content, and support silicon bringup and yield analysis.
Requirements
A bachelor's or master's degree and seven years of experience in DFT or DFT verification are required, along with experience using industry-standard DFT tools or verification flows. Candidates should have strong knowledge of scan or MBIST, JTAG and IEEE standards, Verilog RTL and gate-level simulation, and effective cross-functional communication skills.
Skills
- Design For Test (DFT)
- Scan Insertion
- Scan Compression
- Memory Built-In Self-Test (MBIST)
- DFT Verification
- JTAG
- IEEE 1500
- IEEE 1687
- Verilog RTL
- Gate-Level Simulation
- Memory Repair
- Silicon Bringup
- Yield Analysis
- Power-Aware Simulation
- Perl
- Python
Visa sponsorship
Not detected in the job text
Categories
- Engineering
- Technology
- Software
Keywords
- CPU
- Design For Test (DFT)
- DFT Architecture
- Scan Insertion
- Scan Compression
- MBIST
- Memory Repair
- JTAG
- IEEE 1500
- IEEE 1687
- Verilog RTL
- Gate-Level Netlists
- EDA Tools
- DFT Verification
- STA
- Physical Design
- Power-Aware Simulation
- Third-Party IP Integration
- Test Content
- Silicon Bringup
- Yield Analysis
- ATE Platforms
- Perl
- Python
- TCL
- System Debug
- Artificial Intelligence Tools