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Added 2 mins ago
Graduate Quotations Engineer
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Full-time
…scheduled, customer dates are achieved, and Customer and Sales Engineer is updated on any changes or alternatives to their…
Added 2 mins ago
Digital Architect – Data - GOAPRDJP00000987
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Technical Director - Principal Groundwater Modeler
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AI Engineer
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Senior Data Engineer
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Co-op ASIC Digital Verification Engineer
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Co-op ASIC Digital Verification Engineer
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Senior Electrical Engineer
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Added 1 hour ago
ToolChain Engineer
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Canada
Full-time
…fully realized in software. We're hiring a Compiler & Toolchain Engineer to accelerate and harden the toolchains and libraries that help unlock the performance of Nuvacore's…
Added 1 hour ago
CPU Verification Engineer
NUVACORE
Markham, ON
Full-time
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to…
Added 1 hour ago
CPU DFT Engineer
NUVACORE
Markham, ON
Full-time
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related…
Added 1 hour ago
CPU Clock Distribution and Custom Clock Design
NUVACORE
Markham, ON
Full-time
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU clock design team, you will architect and deliver the clock…

NUVACORE

CPU DFT Engineer

Markham, ON, Canada

Pay: $140,000 to $250,000 USD / year
Job type: Full-time
Apply by: Oct 28, 2026
Experience: BS or MS with 7 years experience in DFT or DFT verification
Posting language: English
Posted: Sep 30, 2026

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Original job description

Full-time

Multiple Levels
Austin and Santa Clara

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.

THE ROLE

As a CPU DFT Engineer, you will participate in the following areas:

Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
Develop scan and BIST insertion flows, implement DFT registers in design blocks
Completing DFT architecture specifications
Review and integrate third party IPs into DFT architecture
Define verification plans for DFT features
Review DFT coverage for scan and MBIST
Verification of DFT features in RTL and gates, and power aware simulations
Generate test content for silicon bringup, and support silicon bringup activities including yield analysis

Requirements - Must To Have

BS or MS with 7 years experience in DFT or DFT verification
Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
Strong understanding of JTAG, IEEE 1500 and IEEE 1687
Experience with Verilog RTL and gate level netlists, including running and debugging simulations
Strong communication skills and ability to work with cross functional teams

Requirements - Nice To Have

Using DFT features to support system debug
Leveraging AI tools to accelerate DFT work flows
Porting test content and supporting silicon bringup on ATE platforms
Experience in perl, python, or TCL

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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More about this job

Responsibilities

Define and implement area- and power-efficient DFT architecture, develop scan and BIST insertion flows, and integrate third-party IP while collaborating with design, STA, and physical design teams. Verify DFT features and coverage, generate silicon test content, and support silicon bringup and yield analysis.

Requirements

A bachelor's or master's degree and seven years of experience in DFT or DFT verification are required, along with experience using industry-standard DFT tools or verification flows. Candidates should have strong knowledge of scan or MBIST, JTAG and IEEE standards, Verilog RTL and gate-level simulation, and effective cross-functional communication skills.

Skills

Design For Test (DFT)
Scan Insertion
Scan Compression
Memory Built-In Self-Test (MBIST)
DFT Verification
JTAG
IEEE 1500
IEEE 1687
Verilog RTL
Gate-Level Simulation
Memory Repair
Silicon Bringup
Yield Analysis
Power-Aware Simulation
Perl
Python

Visa sponsorship

Not detected in the job text

Keywords

CPU
Design For Test (DFT)
DFT Architecture
Scan Insertion
Scan Compression
MBIST
Memory Repair
JTAG
IEEE 1500
IEEE 1687
Verilog RTL
Gate-Level Netlists
EDA Tools
DFT Verification
STA
Physical Design
Power-Aware Simulation
Third-Party IP Integration
Test Content
Silicon Bringup
Yield Analysis
ATE Platforms
Perl
Python
TCL
System Debug
Artificial Intelligence Tools

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