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NUVACORE

CPU DFT Engineer

Markham, ON, Canada

Pay: $140,000 - $250,000 a year
Job type: Full-time
Experience: BS or MS with 7 years experience in DFT or DFT verification
Posting language: English
Posted: Sep 8, 2026

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Original job description

Full-time · Multiple Levels · Austin and Santa Clara

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.

THE ROLE

As a CPU DFT Engineer, you will participate in the following areas:

Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
Develop scan and BIST insertion flows, implement DFT registers in design blocks
Completing DFT architecture specifications
Review and integrate third party IPs into DFT architecture
Define verification plans for DFT features
Review DFT coverage for scan and MBIST
Verification of DFT features in RTL and gates, and power aware simulations
Generate test content for silicon bringup, and support silicon bringup activities including yield analysis

REQUIREMENTS - MUST TO HAVE

BS or MS with 7 years experience in DFT or DFT verification
Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
Strong understanding of JTAG, IEEE 1500 and IEEE 1687
Experience with Verilog RTL and gate level netlists, including running and debugging simulations
Strong communication skills and ability to work with cross functional teams

REQUIREMENTS - NICE TO HAVE

Using DFT features to support system debug
Leveraging AI tools to accelerate DFT work flows
Porting test content and supporting silicon bringup on ATE platforms
Experience in perl, python, or TCL

\n\n

$140,000 - $250,000 a year

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More about this job

Responsibilities

You will define and implement area and power-efficient DFT architectures while collaborating with design, STA, and PD teams. Additionally, you will be responsible for verification of DFT features, generating test content for silicon bringup, and supporting yield analysis.

Requirements

Candidates must have a BS or MS degree with at least 7 years of experience in DFT or DFT verification. Strong proficiency in scan or MBIST flows, industry-standard EDA tools, and RTL/gate-level simulation debugging is required.

Skills

DFT
Scan
MBIST
Verilog
RTL
Gate level netlists
JTAG
IEEE 1500
IEEE 1687
EDA tools
Silicon bringup
Yield analysis
Perl
Python
TCL
Power aware simulations

Visa sponsorship

Not detected in the job text

Keywords

CPU
DFT
Pre-silicon
Post-silicon
Scan
BIST
MBIST
STA
PD
RTL
Gate level netlists
JTAG
IEEE 1500
IEEE 1687
EDA tools
Silicon bringup
Yield analysis
Verilog
Perl
Python
TCL
Power aware simulations
System debug
ATE platforms
Memory repair

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