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NUVACORE

CPU Verification Engineer

  • Markham, ON, Canada

$140,000 to $250,000 USD / year · Full-time

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The original listing is kept below for reference.

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Job details

Pay
$140,000 to $250,000 USD / year
Job type
Full-time
Closing date
Experience
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Posting language
English
Posted

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Original job description

Archived listing. The details below describe a past opening.

Full-time

  • Multiple Levels
  • US / Canada


Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

  • Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
  • Environment Setup: Build, maintain, and scale robust verification environments - stimulus generators, checkers, transactors, and coverage - that exercise the pipeline end to end.
  • Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
  • Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
  • Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
  • Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.


Requirements - Must Have

  • Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
  • 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
  • Strong knowledge of CPU micro-architecture and digital logic - pipelines, out-of-order execution, and branch prediction.
  • Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
  • Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
  • Experience writing and debugging tests in assembly for CPU verification.


Requirements - Nice To Have

  • Experience on one or more of Front-end / execution-unit verification, load/store cache verification, SoC/System verification, Debug/Power mgmt verification.
  • Random instruction sequence (RIS) stimulus generation.
  • Constrained-random verification and coverage-driven closure.
  • Assertions and formal verification.
  • Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
  • Driving a verification problem end-to-end to sign-off.


We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
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More about this job

Responsibilities

Develop CPU verification strategies, test plans, environments, stimulus, checkers, and coverage to identify design bugs and verify pipeline behavior. Collaborate with architecture and RTL teams to debug failures, assess performance, close coverage, and support emulation, FPGA, and silicon bring-up.

Requirements

Requires a degree in Electrical or Computer Engineering, Computer Science, or equivalent practical experience, plus 4+ years of design-verification experience for Senior Engineer or 15+ years for Principal level. Candidates should have strong CPU microarchitecture and functional-verification expertise, proficiency in C/C++ and/or SystemVerilog and scripting, and experience writing and debugging CPU assembly tests.

Skills

  • CPU Microarchitecture
  • Design Verification
  • Digital Logic
  • Out-Of-Order Execution
  • Branch Prediction
  • SystemVerilog
  • C/C++
  • Python
  • Assembly Programming
  • Test Planning
  • Testbench Development
  • Functional Coverage
  • Constrained-Random Verification
  • Assertions
  • Formal Verification
  • Emulation and FPGA Debug

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Categories

  • Engineering
  • Technology
  • Software

Keywords

  • CPU
  • Design Verification
  • CPU Microarchitecture
  • Digital Logic
  • Pipeline
  • Out-Of-Order Execution
  • Branch Prediction
  • SystemVerilog
  • C/C++
  • Python
  • Perl
  • Assembly
  • Random Instruction Sequences
  • Test Plans
  • Testbenches
  • Checkers
  • Transactors
  • Functional Coverage
  • Constrained-Random Verification
  • Coverage-Driven Closure
  • Assertions
  • Formal Verification
  • Performance Models
  • Emulation
  • FPGA
  • Silicon Bring-Up
  • Waveforms
  • Trace
  • Load/Store Cache
  • SoC/System Verification

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