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Added 25 mins ago
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CPU Verification Engineer
NUVACORE
Markham, ON
Full-time
…Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you…
Added 3 hours ago
Formal Verification Engineer
NUVACORE
Markham, ON
Full-time
…Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the Nuvacore CPU correct with formal methods. As part of the design verification (DV)…

NUVACORE

CPU Verification Engineer

Markham, ON, Canada

Pay: $140,000 - $250,000 a year
Job type: Full-time
Experience: 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Posting language: English
Posted: Sep 18, 2026

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Original job description

Full-time · Multiple Levels · US / Canada

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
Environment Setup: Build, maintain, and scale robust verification environments - stimulus generators, checkers, transactors, and coverage - that exercise the pipeline end to end.
Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS - MUST HAVE

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU micro-architecture and digital logic - pipelines, out-of-order execution, and branch prediction.
Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.

REQUIREMENTS - NICE TO HAVE

Experience on one or more of Front-end / execution-unit verification, load/store cache verification, SoC/System verification, Debug/Power mgmt verification.
Random instruction sequence (RIS) stimulus generation.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
Driving a verification problem end-to-end to sign-off.

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$140,000 - $250,000 a year

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More about this job

Responsibilities

You will drive the verification strategy, test plans, and environment development for high-performance CPU designs. Additionally, you will collaborate with architecture and RTL teams to debug complex issues and ensure coverage closure before silicon.

Requirements

Candidates must have a degree in Electrical/Computer Engineering or Computer Science with significant experience in CPU or complex digital design verification. Proficiency in C/C++, SystemVerilog, and assembly language is required for this role.

Skills

CPU Verification
SystemVerilog
C
C++
Python
Perl
Micro-architecture
Digital Logic
RTL Design
Functional Verification
Testbench Development
Assembly
Coverage-driven Closure
Emulation
FPGA
Silicon Bring-up

Visa sponsorship

Not detected in the job text

Keywords

CPU
Verification
RTL
SystemVerilog
C
C++
Python
Perl
Micro-architecture
Pipeline
Out-of-order execution
Branch prediction
Functional verification
Testbench
Assembly
Coverage
Emulation
FPGA
Silicon bring-up
Debugging
Hardware verification
Digital logic
RIS
Constrained-random verification
Formal verification
SoC
Power management
Design verification
Architecture
Hardware engineering

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