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Added 5 mins ago
Quality Engineer
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Contract
The client is looking for a QE Engineer who is strong in test automation, Playwright, and AI/agentic testing, with retail industry experience. The role is focused more on hands-on execution…
Added 5 mins ago
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Full-time
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Added 21 mins ago
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$80,000 to $120,000 CAD / year
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Added 34 mins ago
Test and Commissioning Engineer
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Added 35 mins ago
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…tapeout schedule. Somewhere along the way, you stopped being the engineer who executes the methodology and became the one who writes it, debugs it when it breaks at 2am, and teaches three…
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Test, debug, and extend other software engineer's code.
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Senior Staff Hardware Validation Engineer
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Added 1 hour ago
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Silicon Validation Engineer
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NUVACORE

ToolChain Engineer

Canada

Pay: $140,000 - $250,000 a year
Job type: Full-time
Experience: 15+ years of professional experience working on compiler internals - frontend, middle-end, or backend - in LLVM and/or GCC
Posting language: English
Posted: Sep 30, 2026

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Original job description

Nuvacore is building ground-up CPU silicon for next-generation compute workloads. Our software organization works at the intersection of CPU architecture, silicon design, firmware, operating systems, toolchains, and platform software - developing the compiler toolchains, OS enablement, firmware, and validation infrastructure that ensure new processor capabilities are fully realized in software. We're hiring a Compiler & Toolchain Engineer to accelerate and harden the toolchains and libraries that help unlock the performance of Nuvacore's processors.

The Role

As a Compiler & Toolchain Engineer, you'll be a core member of the team building and maintaining Nuvacore's compiler and toolchain stack across GCC and LLVM along with core libraries and runtime environments. You'll work close to the metal - implementing machine models for our microarchitecture, chasing down codegen correctness and performance issues, and partnering directly with CPU architects to extract every bit of performance possible. You will work closely with our performance engineers to develop an understanding of key performance issues in real-world applications and strategies for optimizing software, libraries and the microarchitecture.

What You'll Own

Design, implement, and maintain compiler backend support (instruction selection, scheduling, register allocation, code generation) for Nuvacore's ISA across GCC and/or LLVM
Diagnose and resolve codegen correctness bugs and performance regressions across the toolchain, from source down to generated machine code
Track and integrate upstream LLVM/GCC changes, and contribute upstream where it benefits the broader ecosystem
Drive toolchain architecture decisions that span the software/hardware boundary and set technical direction for the compiler team
Performance optimization of system libraries and dynamic language environments

Requirements - Must Have

15+ years of professional experience working on compiler internals - frontend, middle-end, or backend - in LLVM and/or GCC
Strong understanding of compiler backend construction: instruction selection, register allocation, instruction scheduling, and code generation
Low-level programming experience targeting x86, ARM, or RISC-V architectures
Proven experience debugging functional and performance issues in large, complex software systems
Experience working within modern, automated software development methodologies (CI/CD, automated testing, code review tooling)
Strong written and verbal communication skills
Demonstrated ability to collaborate across functional teams and work flexibly across domains (compiler, architecture, firmware)
Experience with performance analysis of large scale system-level applications including JIT environments and multiple languages

Requirements - Nice to Have

Upstream contributions to LLVM, GCC, or binutils
Compiler-level performance optimization tuned to a specific microarchitecture
Experience with simulators or instruction set simulators (QEMU, ISS) for toolchain bring-up and validation
Experience bringing up a toolchain for new silicon, from pre-tapeout simulation through post-silicon validation
Prior experience at a CPU or silicon design company

What Success Looks Like

Development of machine models for the Nuvacore microarchitecture
Meaningful performance analysis and optimization of key workloads
Toolchain regressions are caught by automated test infrastructure before they reach downstream firmware or OS teams
Architecture and firmware teams treat you as a trusted technical partner on compiler-related design tradeoffs

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$140,000 - $250,000 a year

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More about this job

Responsibilities

You will design, implement, and maintain compiler backend support for Nuvacore's ISA across GCC and LLVM. Additionally, you will diagnose codegen bugs and collaborate with CPU architects to optimize performance for real-world applications.

Requirements

Candidates must have 15+ years of professional experience in compiler internals and strong proficiency in LLVM or GCC. You should also possess low-level programming experience and the ability to work effectively within automated software development environments.

Skills

Compiler internals
LLVM
GCC
Instruction selection
Register allocation
Instruction scheduling
Code generation
x86
ARM
RISC-V
Performance analysis
CI/CD
Firmware
System libraries
Microarchitecture
Debugging

Visa sponsorship

Not detected in the job text

Keywords

Compiler
Toolchain
CPU
Silicon
LLVM
GCC
ISA
Microarchitecture
Firmware
Performance optimization
x86
ARM
RISC-V
CI/CD
Debugging
System libraries
JIT
Binutils
QEMU
ISS
Software engineering
Backend
Instruction set
Code generation
Register allocation
Instruction scheduling
Validation
Compute workloads
Operating systems
Platform software

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