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Senior Verification Engineer – High Speed Coherent Interconnect Hub

  • Toronto, ON, Canada
  • Canada, Toronto, Canada

The base salary range is 125,000 CAD - 175,000 CAD for Level 3, and 155,000 CAD - 205,000 CAD for Level 4. · Full-time

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Job details

Pay
The base salary range is 125,000 CAD - 175,000 CAD for Level 3, and 155,000 CAD - 205,000 CAD for Level 4.
Job type
Full-time
Experience
3+ years of ASIC verification experience with complex IPs or SoC subsystems.
Posting language
English
Posted

Original job description

NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next generation of scalable, high-performance, multi-chip computing platforms. In this role, you will work closely with architecture and design teams to verify complex High Speed Coherent Interconnect Hub IP. You will help define verification strategies, develop robust verification environments, drive functional and performance verification, close coverage, and ensure high-quality design signoff. This position provides an opportunity to work on technologies at the heart of NVIDIA's next-generation computing platforms.


What You’ll Be Doing:

  • Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus.
  • Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other key IP features.
  • Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
  • Develop and complete performance test plans to validate bandwidth, latency, QoS, and other performance requirements.
  • Drive functional and code coverage closure and toward verification signoff.
  • Debug complex RTL and verification issues and work closely with architecture and design teams to drive them to resolution.
  • Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up.

What We Need to See:

  • BS / MS or equivalent experience.
  • 3+ years of ASIC verification experience with complex IPs or SoC subsystems.
  • Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies.
  • Experience developing verification environments, checkers, assertions, and functional coverage.
  • Strong debugging and problem-solving skills with experience using industry-standard simulation and debug tools.

Ways to Stand Out from the Crowd:

  • Experience verifying high-speed coherent interconnects, NoCs, or other complex SoC infrastructure IP.
  • Knowledge of coherent interconnect protocols and technologies such as CHI and AXI.
  • Strong understanding of cache coherency, transaction ordering, and system-level data flows.
  • Experience with performance verification, including bandwidth, latency, QoS, and traffic management.
  • Strong scripting skills in Python, Perl, or Shell, along with excellent communication and collaboration skills.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology?


Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 125,000 CAD - 175,000 CAD for Level 3, and 155,000 CAD - 205,000 CAD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

More about this job

Responsibilities

Develop and maintain verification infrastructure including testbenches, checkers, and monitors to validate complex High Speed Coherent Interconnect Hub IP. Collaborate with architecture, design, and system validation teams to drive functional and performance verification to signoff.

Requirements

Requires a BS/MS degree or equivalent experience with at least 3 years of ASIC verification experience. Candidates must have a strong background in SystemVerilog, UVM, and coverage-driven verification methodologies.

Skills

  • SystemVerilog
  • UVM
  • Constrained-random verification
  • Coverage-driven verification
  • ASIC verification
  • RTL debugging
  • Protocol compliance
  • Performance verification
  • CHI
  • AXI
  • Cache coherency
  • Python
  • Perl
  • Shell
  • Interconnect verification

Benefits

  • Competitive salary
  • Equity
  • Generous benefits package

Visa sponsorship

Not detected in the job text

Categories

  • Technology
  • Engineering
  • Software

Keywords

  • ASIC
  • SoC
  • Verification
  • SystemVerilog
  • UVM
  • Coherent Interconnect
  • CHI
  • AXI
  • RTL
  • FPGA
  • Emulation
  • Python
  • Perl
  • Shell
  • Bandwidth
  • Latency
  • QoS
  • Cache Coherency
  • Silicon Bring-up
  • Performance Verification
  • Functional Coverage
  • Code Coverage
  • Constrained-random
  • Interconnect Hub
  • Tegra

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