ASIC Design Lead

ASIC Design Lead

Company: O-HIVE Inc.

Location: Windsor, Ontario, Canada

Employment Type: Full-Time

Department: Semiconductor Engineering / AI Hardware

Seniority: Senior / Technical Lead

About O-HIVE

O-HIVE is an AI and spatial vision technology company developing Visual Language Model (VLM)-powered solutions for industrial automation, robotics, autonomous systems, and intelligent vision applications.

Our technology enables machines to perceive, understand, and interact with physical environments through advanced computer vision, spatial intelligence, and edge AI.

We are expanding our semiconductor development capabilities to build a next-generation Spatial Vision Intelligence Chip (SVIC), an ultra-compact, power-efficient ASIC designed to accelerate visual perception, object detection, spatial mapping, pose estimation, navigation, and VLM inference.

Our targeted semiconductor architecture uses advanced 4 nm process technology and integrates dedicated AI accelerators with programmable FPGA components and embedded processing capabilities.

Role Overview

We are seeking an experienced and hands-on ASIC Design Lead to lead the architecture, RTL development, verification, and implementation of O-HIVE's next-generation spatial vision and AI inference accelerator.

The ideal candidate has extensive experience in digital ASIC design, SoC architecture, FPGA prototyping, and semiconductor development, with the ability to translate complex AI and computer vision algorithms into efficient hardware implementations.

This role will take technical ownership of the ASIC development lifecycle, from initial architectural specifications and microarchitecture design through RTL implementation, functional verification, physical design coordination, tape-out, and silicon validation.

The ASIC Design Lead will collaborate closely with AI researchers, VLM engineers, FPGA engineers, system architects, and semiconductor manufacturing partners to develop a highly integrated, low-power AI processor for robotics, autonomous navigation, industrial inspection, and embedded vision applications.

Key Responsibilities1. ASIC Architecture & Microarchitecture

• Lead the definition and development of digital ASIC architecture for spatial vision intelligence and edge AI acceleration.
• Translate AI, computer vision, and spatial perception workloads into hardware architectures suitable for ASIC implementation.
• Design specialized accelerators for feature extraction, visual mapping, pose estimation, object detection, navigation, and VLM inference.
• Define datapaths, memory hierarchies, processing pipelines, interconnects, and hardware interfaces.
• Develop microarchitecture specifications, functional block diagrams, and detailed design documentation.
• Evaluate design tradeoffs involving performance, power consumption, silicon area, memory bandwidth, and implementation complexity.
• Work with AI engineering teams to optimize neural network computation, quantization, and hardware inference efficiency.

2. RTL Design & Development

• Lead and perform RTL design using SystemVerilog and Verilog.
• Develop synthesizable RTL modules for AI accelerators, control logic, memory interfaces, and high-performance processing engines.
• Design and integrate reusable RTL IP blocks.
• Implement efficient pipelined, parallel, and low-power processing architectures.
• Perform RTL code reviews, design optimization, and technical debugging.
• Establish RTL coding standards, design methodologies, and version-control practices.
• Ensure design compatibility with synthesis, verification, and downstream physical implementation requirements.

3. Functional Verification & Validation

• Develop comprehensive ASIC verification strategies and test plans.
• Lead simulation-based verification using SystemVerilog, UVM, and industry-standard verification tools.
• Implement testbenches, assertions, coverage models, and regression testing environments.
• Perform functional verification, formal verification, and equivalence checking where appropriate.
• Identify and resolve RTL functional defects and integration issues.
• Coordinate clock-domain crossing, reset-domain crossing, and timing-related verification.
• Establish verification sign-off criteria before physical implementation and tape-out.

4. Physical Design & Tape-Out

• Coordinate ASIC implementation activities, including logic synthesis, floorplanning, placement, clock-tree synthesis, routing, and timing closure.
• Work with internal engineers and external semiconductor partners to meet power, performance, and area (PPA) targets.
• Support static timing analysis, power analysis, design rule checking, and layout-versus-schematic verification.
• Coordinate design-for-test (DFT) planning, scan insertion, ATPG, and manufacturing test readiness.
• Support advanced-node semiconductor development, targeting 4 nm process technology.
• Manage design readiness, engineering reviews, sign-off requirements, and tape-out deliverables.
• Collaborate with foundries, IP suppliers, packaging vendors, and manufacturing partners.
• Support post-silicon bring-up, debugging, characterization, and production validation.

5. FPGA Prototyping & Hardware Integration

• Develop and validate ASIC functionality through FPGA prototyping platforms.
• Collaborate with FPGA engineers to transition proven FPGA-based designs into ASIC implementations.
• Support the integration of image sensor interfaces, embedded processors, memory, and communication subsystems.
• Work with system engineers on MIPI CSI-2, sensor preprocessing, IMU integration, and high-speed digital interfaces.
• Develop hardware/software integration and validation strategies.
• Support system-level performance testing with robotics, autonomous platforms, and machine vision applications.
• Ensure architectural consistency between ASIC accelerators, FPGA subsystems, and embedded control software.

6. AI & Computer Vision Hardware Acceleration

• Collaborate with AI and computer vision teams to accelerate spatial perception and VLM workloads directly in hardware.
• Develop hardware processing architectures supporting visual feature extraction, matching, mapping, and localization.
• Optimize neural network execution for object detection and visual understanding.
• Support low-precision arithmetic, parallel computation, efficient memory access, and power-aware inference.
• Evaluate ASIC acceleration strategies for SLAM, real-time object detection, and compact VLM architectures.
• Develop performance benchmarks and verification methodologies to compare ASIC, FPGA, CPU, and GPU implementations.
• Identify architectural opportunities to reduce memory movement, compute latency, and overall energy consumption.

7. Technical Leadership & Project Management

• Lead ASIC development activities across architecture, RTL, verification, and implementation.
• Establish technical milestones, engineering deliverables, and development schedules.
• Mentor ASIC and FPGA engineers and conduct technical design reviews.
• Coordinate with internal teams and external engineering contractors.
• Identify technical risks and develop mitigation strategies.
• Maintain technical documentation, specifications, design records, and validation reports.
• Provide engineering progress updates and communicate technical decisions to company leadership.
• Support semiconductor vendor evaluation, IP selection, and manufacturing partner coordination.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related technical field.
• 7+ years of professional experience in digital ASIC design, SoC development, or semiconductor engineering.
• Strong hands-on experience developing synthesizable RTL using SystemVerilog or Verilog.
• Demonstrated experience with ASIC architecture, microarchitecture, and hardware implementation.
• Experience with ASIC functional verification, simulation, debugging, and verification methodologies.
• Strong understanding of digital logic, pipelining, finite-state machines, memory architectures, and hardware interfaces.
• Experience with logic synthesis, static timing analysis, and physical design constraints.
• Familiarity with semiconductor design and implementation tools from Synopsys, Cadence, or Siemens EDA.
• Experience with FPGA design, prototyping, or ASIC-to-FPGA design validation.
• Solid understanding of semiconductor design flows from RTL development through tape-out.
• Experience collaborating with cross-functional hardware, software, and systems engineering teams.
• Strong analytical, debugging, documentation, and technical problem-solving skills.
• Ability to take ownership of complex semiconductor engineering tasks and work independently.

Preferred Qualifications

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline.
• Prior technical leadership experience on an ASIC or SoC development program.
• Experience with at least one completed ASIC tape-out and post-silicon validation.
• Experience with advanced semiconductor process nodes, including 7 nm, 5 nm, or 4 nm.
• Experience designing AI inference accelerators, NPUs, DSP