About O-HIVE
O-HIVE is a technology company developing next-generation Visual Language Model (VLM) intelligence, spatial vision systems, and specialized AI semiconductors for robotics, industrial automation, and autonomous systems.
Our technology enables machines to perceive their surroundings, recognize objects, understand spatial relationships, and make intelligent decisions in real time. By combining advanced computer vision, 3D spatial processing, and edge AI acceleration, O-HIVE is building compact, high-performance computing solutions that operate directly on embedded hardware.
We are developing a dedicated Spatial Vision ASIC architecture that integrates visual feature extraction, mapping, pose estimation, object detection, and VLM inference into an energy-efficient semiconductor platform.
Position Overview
We are seeking a talented and motivated FPGA Engineer to join our engineering team and contribute to the development of hardware-accelerated spatial vision and edge AI systems.
The successful candidate will design, implement, and optimize FPGA-based processing architectures for real-time computer vision, simultaneous localization and mapping (SLAM), object detection, and AI inference.
This position involves working closely with AI researchers, software engineers, embedded systems developers, and ASIC designers to transition computationally intensive algorithms into efficient hardware implementations.
The engineer will play an important role in developing FPGA prototypes and supporting their eventual transition into production ASIC designs.
Key Responsibilities1. FPGA Architecture & RTL Development
- Design and implement FPGA-based accelerators using Verilog, SystemVerilog, VHDL, or High-Level Synthesis (HLS).
- Develop efficient hardware processing pipelines for real-time image processing and AI workloads.
- Optimize FPGA designs for latency, throughput, power consumption, and resource utilization.
- Implement memory interfaces, hardware buffers, data movement architectures, and parallel processing pipelines.
- Perform functional simulation, synthesis, timing analysis, and hardware verification.
2. Spatial Vision & SLAM Acceleration
- Develop hardware acceleration for visual feature extraction, including FAST, ORB, and related computer vision algorithms.
- Implement FPGA-based image preprocessing, feature matching, and geometric computation.
- Support hardware acceleration of visual odometry, mapping, and camera pose estimation.
- Integrate FPGA processing pipelines with SLAM frameworks such as ORB-SLAM3.
- Develop low-latency processing architectures for real-time navigation and 3D spatial awareness.
3. AI & VLM Hardware Acceleration
- Work with AI engineering teams to implement hardware-accelerated object detection and visual intelligence workloads.
- Support the deployment and optimization of YOLO-family detection models and lightweight VLM architectures.
- Develop efficient data paths for neural network computation and inference.
- Explore quantization and reduced-precision computation techniques, including INT8, INT4, and FP8.
- Optimize parallel computation, memory access, and accelerator utilization for resource-constrained edge devices.
4. Camera & Sensor Integration
- Develop FPGA interfaces for CMOS image sensors using MIPI CSI-2 and other high-speed interfaces.
- Implement image sensor control, pixel processing, frame buffering, and image data pipelines.
- Integrate inertial measurement units (IMUs) and other sensors into spatial vision processing architectures.
- Develop hardware-level timestamp synchronization between image frames and motion sensor data.
- Support real-time image correction, filtering, and preprocessing.
- Collaborate on sensor-to-FPGA-to-ASIC data flow and system integration.
5. FPGA Prototyping & ASIC Development
- Develop and validate FPGA prototypes of O-HIVE's Spatial Vision ASIC architecture.
- Work with ASIC engineers to translate validated FPGA processing blocks into ASIC-compatible RTL designs.
- Support functional verification, performance benchmarking, and design optimization.
- Participate in architectural reviews and hardware/software partitioning decisions.
- Document hardware modules, interfaces, performance characteristics, and design specifications.
6. Hardware Testing & Performance Optimization
- Develop testbenches and hardware validation procedures.
- Debug FPGA designs using simulation, logic analyzers, and hardware debugging tools.
- Benchmark processing latency, throughput, power consumption, and hardware resource utilization.
- Identify and resolve bottlenecks in processing pipelines and memory bandwidth.
- Support integration testing with embedded CPUs, sensors, and external processing modules.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
- Practical experience developing FPGA designs using Verilog, SystemVerilog, or VHDL.
- Familiarity with AMD/Xilinx or Intel/Altera FPGA development environments.
- Experience with FPGA synthesis, implementation, timing closure, and debugging.
- Understanding of digital logic design, pipelining, parallel processing, and memory architecture.
- Proficiency in C/C++ or Python for testing, simulation, and hardware integration.
- Knowledge of embedded systems and hardware/software interfaces.
- Strong analytical, debugging, and problem-solving skills.
- Ability to work collaboratively in a multidisciplinary engineering team.
Preferred Qualifications
- Experience with AMD Vivado, Vitis, or Vitis HLS.
- Experience using AMD Zynq UltraScale+ MPSoC, Kria, or comparable FPGA platforms.
- Experience implementing image processing or computer vision algorithms on FPGA.
- Familiarity with SLAM, visual odometry, ORB feature extraction, or feature matching.
- Knowledge of CNN accelerators, neural network inference, or edge AI hardware.
- Experience with MIPI CSI-2, AXI, DDR memory controllers, or high-speed sensor interfaces.
- Experience with real-time sensor synchronization involving cameras and IMUs.
- Knowledge of fixed-point arithmetic, quantization, and hardware optimization.
- Familiarity with ASIC design flows and FPGA-to-ASIC migration.
- Experience with power-efficient embedded architectures and semiconductor development.
- Familiarity with robotics platforms, ROS/ROS2, and autonomous systems.
What We Offer
- Opportunity to contribute directly to the development of next-generation Spatial Vision ASIC technology.
- Hands-on experience building real hardware acceleration systems for visual intelligence.
- Exposure to the complete development process, from FPGA prototyping to ASIC implementation.
- Collaboration with international engineering teams across North America and Asia.
- Opportunities to work on industrial robotics, autonomous systems, embedded AI, and advanced semiconductor technologies.
- A technically challenging environment with meaningful ownership of engineering deliverables.
- Professional growth opportunities in FPGA architecture, hardware acceleration, and AI semiconductor engineering.
