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PRI Global

Principal Hardware Engineer

Ottawa, ON, Canada

Job type: Contract
Apply by: Oct 31, 2026
Experience: 7+ years of FPGA design experience in wireless or high-speed systems.
Posting language: English
Posted: Oct 1, 2026

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Original job description

Works on unusually complex problems and provides highly innovative solutions Uses independent judgment to accomplish goals and objectives Has insight into industry trends and communicates vision to guide organizational strategy and long-range planning Lends research and contributes to evaluations, project plans and budgets for new products or updates existing products Acts as consultant on critical projects that impact long term organizational goals and objectives Leads teams, gives technical guidance and communicates with senior management on progress Identifies or creates solutions that are likely to contribute to the development of new company concepts Expected to set standards and achieve cost targets for product cost through proper design choices, component selection or supplier selection Demonstrated expertise in competitive analysis May actively seek customer input and take responsibility for internal and external customer situations Determines requirements and functional specifications for entire system, under only consultative directionDescription Comments:

This is Onsite in Ontario Ottawa

What You’ll Do

Design & Architecture:

Develop FPGA IP architecture for 4G/5G Radio Units.

Contribute to system-level design aligned with 3GPP and O-RAN Alliance specifications.

Implementation:

Implement complex RTL blocks (Verilog/SystemVerilog/VHDL) and integrate into larger systems.

Optimize FPGA resource utilization and ensure timing closure.

Validation & Testing:

Define and execute verification plans using UVM and advanced techniques.

Perform simulation and system-level FPGA validation.

Collaboration:

Work closely with Radio Unit development teams for seamless integration.

Partner with software teams to ensure hardware-software interoperability.

Mentor junior engineers and participate in technical reviews.

Essential Requirements:

Proven experience in FPGA design and RTL development.

Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing.

Familiarity with JESD204B/C, Ethernet, PCIe, AXI, and high-speed SERDES.

Tools: Quartus, Vivado, MATLAB/Simulink, HDL Coder.

Knowledge of UVM and verification methodologies.

Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.

Experience with Git/GitHub and version control workflows.

Desirable Skills:

7+ years of FPGA design experience in wireless or high-speed systems.

Experience in high-volume wireless products and IP development.

Contributions to standards bodies or technical forums (O-RAN, 3GPP).

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More about this job

Responsibilities

Design FPGA IP architecture and complex RTL for 4G/5G radio units, integrating systems to industry specifications and optimizing FPGA resources and timing. Lead verification and validation, collaborate with hardware and software teams, mentor engineers, and provide technical guidance on critical projects.

Requirements

Requires proven FPGA design and RTL development experience, knowledge of 4G/5G radio architecture, O-RAN, wireless protocols, signal processing, and verification methodologies. Familiarity with Quartus, Vivado, MATLAB/Simulink, HDL Coder, version control, and high-speed interfaces is expected; 7+ years of relevant experience is desirable.

Skills

FPGA Design
RTL Development
Verilog
SystemVerilog
VHDL
FPGA Architecture
UVM Verification
4G/5G Radio Architecture
O-RAN
NR/LTE Protocols
eCPRI/CPRI
Signal Processing
JESD204B/C
High-Speed SERDES
Timing Closure
Technical Leadership

Visa sponsorship

Not detected in the job text

Keywords

FPGA
RTL
Verilog
SystemVerilog
VHDL
4G
5G
3GPP
O-RAN Alliance
NR
LTE
eCPRI
CPRI
PTP
Signal Processing
JESD204B/C
Ethernet
PCIe
AXI
SERDES
Quartus
Vivado
MATLAB/Simulink
HDL Coder
UVM
Git
GitHub
Timing Closure
Radio Units
FPGA Validation

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