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Added 1 hour ago
IH
Senior Platform Database RUN Engineer
InVita Healthcare Technologies
ON · Ontario, Canada
- Full-time
Job Title: Senior Platform Database RUN Engineer
Added 1 hour ago
IH
Platform Database RUN Engineer
InVita Healthcare Technologies
ON · Ontario, Canada
- Full-time
Extensive experience in database related software development;
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Senior Naval Architect - Team Lead
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Qualcomm

ASIC/FPGA Design Verification Engineer, Senior

Ottawa, ON, Canada

$108,000.00 - $158,000.00 · Full-time

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Applications open in a new tab.

Job details

Pay: $108,000.00 - $158,000.00
Job type: Full-time
Posting language: English
Posted: Oct 9, 2026

Original job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Replacement Position

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Senior ASIC/FPGA Design Verification Engineer

What You’ll Do          

Deliver standards-compliant IP blocks for use in OTN / Ethernet / CXL / PCIE/ UALink/ UEC FPGAs or ASICs.

Lead ASIC or FPGA projects

Streamline ASIC development process with advancing tools/scripting.

Architect, develop and document the verification environment using SystemVerilog + UVM

Develop test plan.

Develop and execute individual test-cases against the RTL

Issue and track bug reports from inception to closure

Working with our external customers and/or internal engineers to verify, validate and deliver designs for use in OTN / Ethernet FPGAs or ASICs

Mentor junior engineers

What You’ll Need

MSc/MEng with 5+ years of experience or BSc/BEng with 7+ years of experience in ASIC or FPGA development

Communications Protocol knowledge (OTN, Ethernet, CXL, PCIE, UALink, UEC etc)

Solid experience with Verilog and SystemVerilog

Experience with simulation tools

Experience in SystemVerilog+UVM

Excellent ability to use Randomized and Directed Verification Methodologies

Experience with Unix/Linux Shell scripting

Experience with source code revisioning systems, SVN, CVS, RCS e.g.

It’d Be Amazing If You Had

Experience in OTN / Ethernet transport systems

Experience in CXL / PCIE

Experience in UALink / UEC

Experience with Debugging Tools

Experience with PERL, TCL, Python and C/C++ programmng

About You

Excellent communication skills

Able to listen to and appreciate ideas and opinions that differ from yours

Extremely detail oriented

Superb analytical and problem-solving skills

Drives for consistency

Takes personal pride in high standard of outputs

Self-motivated and self-managing

Mentoring and coaching skills

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Pay range and Other Compensation & Benefits:

$108,000.00 - $158,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.

Apply About employer

More about this job

Responsibilities

You will define, model, design, and verify high-performance IP blocks for ASIC and FPGA projects. Additionally, you will lead project execution, develop test plans, and mentor junior engineers.

Requirements

The role requires a Bachelor's or Master's degree in Engineering or a related field with at least 5 to 7 years of relevant experience. Candidates must possess strong knowledge of communication protocols and proficiency in SystemVerilog and UVM.

Skills

ASIC design
FPGA development
SystemVerilog
UVM
Verilog
OTN
Ethernet
CXL
PCIE
UALink
UEC
Unix/Linux shell scripting
Randomized verification
Directed verification
Debugging tools
C++

Benefits

Annual discretionary bonus program
Annual RSU grants
Competitive benefits package

Visa sponsorship

Not detected in the job text

Keywords

ASIC
FPGA
Design Verification
SystemVerilog
UVM
Verilog
OTN
Ethernet
CXL
PCIE
UALink
UEC
RTL
Unix
Linux
Shell scripting
SVN
CVS
RCS
Perl
TCL
Python
C++
SoC
IP development
Validation
Integration
Randomized verification
Directed verification
Debugging

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