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DFT Engineer, Principal

  • Toronto, ON, Canada

Full-time

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Job details

Job type
Full-time
Posting language
English
Posted

Original job description


Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm DFT Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

What You'll Do

  • Acting as a member of Qualcomm's central DFT methodology group responsible for developing, maintaining and supporting flows across all company business units and projects
  • Architecting methodologies and flows for an integrated, RTL centric "shift left" DFT environment across company IPs, ASICs and SoC designs.
  • Writing and automating RTL for advanced DFT and DFD features not currently supported by the EDA vendors
  • Developing automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
  • Building IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
  • Writing static timing constraints, creating waivers and devising flows for bullet proof timing checks.
  • New Position

What You'll Need:

  • Bachelor's degree in engineering science, Electrical and Computer Engineering or Computer Science
  • 10+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
  • Vast experience with various DFT EDA tools from Siemens, SNPS and Cadence
  • Good knowledge and understanding in Verilog/VHDL and SystemVerilog
  • Exposure to CAD and automation. Good exposure for using de-Perl techniques in creating generic codes. Knowledge of TCL and Python is a plus.
  • Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
  • Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs is highly desirable.
  • Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers.

More about this job

Responsibilities

Develop and maintain central DFT methodologies and flows for integrated RTL-centric environments across company IPs and SoCs. Architect end-to-end verification solutions and automate RTL for advanced DFT and DFD features.

Requirements

Requires a degree in Electrical/Computer Engineering or Computer Science with 10+ years of experience in complex SoC designs. Must have extensive experience with DFT EDA tools and standards such as JTAG, iJTAG, and BIST techniques.

Skills

  • DFT
  • RTL
  • SystemVerilog
  • Verilog
  • VHDL
  • TCL
  • Python
  • Perl
  • JTAG
  • iJTAG
  • BIST
  • ATPG
  • SoC Design
  • Static Timing Analysis
  • EDA Tools
  • FPGA

Visa sponsorship

Not detected in the job text

Categories

  • Engineering
  • Technology
  • Software
  • Manufacturing
  • Science & Research

Keywords

  • DFT
  • DFD
  • RTL
  • SoC
  • CoWoS
  • JTAG
  • iJTAG
  • BIST
  • ATPG
  • SystemVerilog
  • Verilog
  • VHDL
  • TCL
  • Python
  • Perl
  • Siemens EDA
  • Synopsys
  • Cadence
  • Static Timing Constraints
  • Scan Insertion
  • Hardware Engineering
  • FPGA
  • DSP
  • Digital Systems
  • Analog Systems
  • RF Systems
  • Optical Systems
  • Verification Test Bench
  • SDF Annotated
  • Zero Delay Simulation

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