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Added 1 month ago
Data Analyst
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Qualcomm

Engineer

Markham, ON, Canada

$90,100.00 - $135,100.00 · Full-time

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Job details

Pay: $90,100.00 - $135,100.00
Job type: Full-time
Experience: 6 months to 2 years of experience in ASIC Physical Design, Digital Design, VLSI, or a related semiconductor domain (including internships or co-op experience).
Posting language: English
Posted: Aug 4, 2026

Original job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

QCT's DSP Physical Design Team is seeking motivated and talented Physical Design Engineer to join our growing team in Markham, Canada. In this role, you will contribute to the implementation of cutting-edge DSP cores used in next-generation mobile, compute, and AI-enabled products. Working alongside experienced engineers, you will gain hands-on exposure to the complete ASIC development cycle, from RTL handoff through physical implementation and tapeout.

This position is ideal for early-career engineers with a strong foundation in VLSI and digital design fundamentals who are passionate about semiconductor technology and eager to build expertise in Physical Design, timing closure, power optimization, and silicon realization. You will collaborate closely with architecture, RTL, verification, DFT, and methodology teams while learning industry-leading design flows, automation techniques, and advanced implementation methodologies.

The role offers excellent opportunities for technical growth, mentorship, and career development while working on complex and high-impact designs in a fast-paced, innovation-driven environment. Candidates with strong engineering fundamentals, problem-solving abilities, and a willingness to learn new technologies will thrive in this position.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Key Responsibilities

Contribute to ASIC Physical Design activities from netlist to GDSII under the guidance of senior engineers.
Support floorplanning, placement, clock tree synthesis, routing, timing analysis, and physical verification tasks.
Analyze and debug timing, congestion, and design rule issues.
Participate in PPA (Power, Performance, Area) analysis and optimization activities.
Assist with ECO implementation, design closure, and tapeout readiness.
Collaborate with RTL, DFT, verification, and methodology teams to resolve design and implementation challenges.
Develop scripts and automation solutions to improve engineering productivity and design quality.
Learn and apply industry best practices for advanced semiconductor design and implementation.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
6 months to 2 years of experience in ASIC Physical Design, Digital Design, VLSI, or a related semiconductor domain (including internships or co-op experience).
Strong understanding of VLSI and digital design fundamentals, including combinational and sequential logic, FSMs, clocking concepts, and timing analysis.
Basic understanding of ASIC design flow from RTL to GDSII.
Familiarity with Physical Design concepts such as floorplanning, placement, CTS, routing, timing analysis, and physical verification.
Exposure to industry-standard EDA tools used for synthesis, implementation, timing analysis, or verification.
Basic scripting skills in Python, Tcl, Perl, or Shell.
Strong analytical, debugging, and problem-solving skills.
Effective communication and teamwork abilities.

Preferred Qualifications

Coursework, academic projects, internship, or industry experience in VLSI, ASIC, Digital Design, or Physical Design.
Familiarity with Verilog/SystemVerilog, RTL design, synthesis, and verification methodologies.
Understanding of STA, DFT fundamentals, low-power design concepts, and silicon implementation flows.
Experience developing automation scripts and productivity tools for engineering workflows.
Familiarity with data analysis, AI-assisted engineering tools, or emerging AI technologies that enhance engineering productivity.
Demonstrated curiosity, learning agility, and passion for semiconductor technology.
Strong ownership mindset and willingness to take on challenging technical problems.

Why Join Us?

Work on industry-leading DSP technologies powering next-generation products.
Gain hands-on experience across the complete ASIC implementation lifecycle.
Develop strong VLSI and Physical Design expertise through mentorship from experienced technical leaders.
Collaborate with world-class teams across architecture, RTL, verification, and implementation.
Learn modern design methodologies, automation techniques, and emerging engineering technologies.
Excellent opportunity for technical growth and long-term career development in semiconductor design.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Pay range and Other Compensation & Benefits:

$90,100.00 - $135,100.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.

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More about this job

Responsibilities

Contribute to ASIC physical design activities from netlist to GDSII, including floorplanning, placement, and timing closure. Collaborate with cross-functional teams to resolve design challenges and develop automation scripts to improve productivity.

Requirements

Requires a Bachelor's or Master's degree in Electrical or Computer Engineering with 6 months to 2 years of experience in ASIC physical design or related domains. Candidates must have a strong foundation in VLSI fundamentals and familiarity with industry-standard EDA tools.

Skills

ASIC Physical Design
VLSI
Digital Design
Floorplanning
Placement
Clock Tree Synthesis
Routing
Timing Analysis
Physical Verification
Python
Tcl
Perl
Shell
Verilog
SystemVerilog
STA

Benefits

Annual discretionary bonus program
Annual RSU grants
Competitive benefits package

Visa sponsorship

Not detected in the job text

Keywords

ASIC
DSP
Physical Design
VLSI
Digital Design
RTL
GDSII
Floorplanning
Placement
Clock Tree Synthesis
Routing
Timing Analysis
Physical Verification
PPA
ECO
DFT
Python
Tcl
Perl
Shell
Verilog
SystemVerilog
STA
Semiconductor
Automation
EDA Tools
AI-assisted engineering

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