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Qualcomm

IC/FPGA Design Verification Engineer, Sr Staff

Ottawa, ON, Canada

Full-time

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Job details

Job type: Full-time
Posting language: English
Posted: Oct 9, 2026

Original job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Replacement Position

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Senior Staff ASIC/FPGA Design Verification Engineer

What You'll Do

Deliver standards-compliant IP blocks and subsystems for PCIe Gen7 (and beyond), CXL 4.0 (and beyond), UALink, Ethernet, and next-generation high-speed interconnect ASICs and FPGAs.

Provide technical leadership for verification activities across IP, subsystem, and system-level designs.

Architect, develop, and document scalable verification environments using SystemVerilog and UVM.

Develop comprehensive verification test plans and drive verification closure.

Develop, debug, and optimize complex test cases to achieve functional and coverage goals.

Drive bug tracking, root-cause analysis, and issue resolution from discovery through closure.

Improve engineering productivity through advanced tools, AI-driven verification techniques, automation, and scripting solutions.

Collaborate closely with architecture, design, software, validation, and customer teams to ensure successful product execution.

Mentor junior and senior engineers, promoting technical excellence and verification best practices across the organization.

What You'll Need

MSc/MEng with 7+ years of experience, or BSc/BEng with 10+ years of experience in ASIC or FPGA development and verification.

Deep knowledge of high-speed communication and interconnect protocols such as PCIe, CXL, UALink, and Ethernet.

Expert-level experience with SystemVerilog, UVM, constrained-random, and coverage-driven verification methodologies.

Strong understanding of IP, subsystem, and SoC-level verification.

Extensive experience with simulation, debugging, verification closure, functional coverage, and assertion-based verification.

Excellent technical leadership, communication, and problem-solving skills.

Ability to influence technical direction and drive alignment across cross-functional teams.

It'd Be Amazing If You Had

Experience with PCIe Gen5/6/7 or CXL 3.0/4.0 from Physical Layer through Transaction Layer.

Experience with UALink and next-generation AI/HPC interconnect technologies.

Experience using PCIe/CXL VIPs from Siemens/Avery, Cadence, or Synopsys.

Experience leveraging AI-based approaches to improve verification productivity, test generation, debug, and coverage closure.

Experience with formal verification, emulation, or FPGA prototyping.

Experience defining or deploying verification methodologies used across multiple projects or teams.

About You

Recognized as a technical leader who drives execution and delivers results.

Strong mentoring and coaching skills with a passion for developing engineers.

Detail-oriented with exceptional analytical and problem-solving abilities.

Committed to engineering excellence, quality, and continuous improvement.

Self-motivated, self-managing, and accountable for project outcomes.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers.

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More about this job

Responsibilities

The Senior Staff Engineer will lead the verification of high-performance IP blocks and subsystems for next-generation interconnect technologies like PCIe Gen7 and CXL 4.0. They will architect scalable verification environments, drive verification closure, and mentor engineering teams to ensure high-quality product execution.

Requirements

Candidates must possess a Bachelor's degree with 10+ years or a Master's degree with 7+ years of experience in ASIC or FPGA development and verification. Expert-level proficiency in SystemVerilog, UVM, and high-speed communication protocols is required for this technical leadership role.

Skills

ASIC Design
FPGA Verification
SystemVerilog
UVM
PCIe
CXL
Ethernet
High-speed Interconnects
Functional Coverage
Assertion-based Verification
Technical Leadership
Debugging
Constraint-random Verification
SoC Verification
AI-driven Verification

Visa sponsorship

Not detected in the job text

Keywords

ASIC
FPGA
Design Verification
PCIe Gen7
CXL 4.0
UALink
Ethernet
SystemVerilog
UVM
SoC
Constrained-random
Coverage-driven
Formal Verification
Emulation
FPGA Prototyping
AI-based Verification
Debugging
Root-cause Analysis
High-speed Interconnect
Technical Leadership
PCIe VIP
CXL VIP
Automation
Scripting
IP Development
Subsystem Verification
Validation
HPC
AI
Qualcomm

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