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Are you a creative engineer looking for challenges?
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Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential…

Qualcomm

Staff Verification Engineer, Compute Subsystems

Markham, ON, Canada

Pay: $129,600.00 - $179,600.00
Job type: Full-time
Posting language: English
Posted: Sep 25, 2026

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Original job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Are you a creative engineer looking for challenges?

Want to develop technologies that improve people’s everyday life?

Qualcomm AI HW team is looking for a strong ASIC design verification engineer.

Join our effort in developing world class ML HW solutions and push the boundaries on features and performance.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

As a member of the team, your responsibilities include:

Work closely with design, architects, and verification leads to develop the multimedia and compute subsystem integration verification strategy and test plan
Create verification environment using UVM/System Verilog
Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
Write tests and regressions to identify any bugs in own work and helps more junior team members do the same
Develop C reference model
Interpret the results of performance checks and identify issues
Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner
Perform RTL code coverage, assertion coverage, functional coverage, and gate level simulations
Employ power aware verification technique to verify low power design features
Identify opportunity for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements

Required Competencies

Thorough understanding of Digital design concepts
Strong UVM, System Verilog skills
Understanding of Bus protocols like AHB/AXI
Perl, python scripting experience
Quick understanding of Specs and Standards and developing relevant and thorough test plans
Experienced in developing monitors, scoreboards, sequencers and sequences and various aspects of the UVM testbenches
Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug
Strong communication skills and works well in a team environment

Qualifications

5+ years ASIC design, verification, or related work experience.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Pay range and Other Compensation & Benefits:

$129,600.00 - $179,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.

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More about this job

Responsibilities

Develop multimedia and compute subsystem integration verification strategies and test plans while creating environments using UVM/System Verilog. Resolve architecture and design problems while driving productivity improvements and adopting new verification methodologies.

Requirements

Requires a degree in Engineering or a related field with 3-5+ years of relevant ASIC design and verification experience. Candidates must possess strong UVM, System Verilog, and scripting skills along with a thorough understanding of digital design concepts.

Skills

ASIC design
Verification
UVM
System Verilog
Digital design
AHB
AXI
Perl
Python
RTL code coverage
Functional coverage
Gate level simulations
Power aware verification
Test planning
C reference model

Benefits

Annual discretionary bonus program
Annual RSU grants
Competitive benefits package

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Verification
UVM
System Verilog
Digital Design
AHB
AXI
Perl
Python
RTL
Functional Coverage
Gate Level Simulation
Power Aware Verification
Compute Subsystems
Machine Learning
Hardware
Integration
Test Plan
Regression
C Reference Model
Architecture
Debugging
Scripting
Productivity Improvement
Multimedia

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