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Added 6 mins ago
MANAGER DEVELOPMENT ENGINEERING
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…including Official Plan Amendments, Zoning By-law Amendments, Site Plan Controls, Plans of Subdivision and Consents. The review focuses on the municipal engineering aspects of the…
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To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency…
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Software Engineer II
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Verification Engineer, Senior
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Toronto, ON
- Full-time
…create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP…
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Qualcomm

Verification Engineer, Senior

Toronto, ON, Canada

$108,000.00 - $158,000.00 · Full-time

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Job details

Pay: $108,000.00 - $158,000.00
Job type: Full-time
Posting language: English
Posted: Oct 26, 2026

Original job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Replacement Position

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

About Our Team

The HSI Digital Design Verification team specializes in high speed SerDes technology, which serves as a fundamental building block for advanced connectivity solutions. Our work enables reliable, high bandwidth communication between compute, memory, storage, and networking components, forming an essential part of the fabric that connects modern AI data centers.

We take pride in supporting one another and delivering results. This is an opportunity to work on meaningful projects, develop advanced technical skills, take on significant responsibilities, and contribute to technology that shapes the future.

What You’ll Do

Review digital design specifications and devise verification plans for design functionality
Understand design implementation and develop testbenches and test cases using SystemVerilog and UVM
Debug and bring up simulations by identifying root causes
Integrate analog behavioral models into verification environments to validate digital and analog mixed signal designs and their interactions
Collaborate with Design, Systems, Firmware, and Analog teams to resolve issues and achieve verification closure
Facilitate bit-matching between RTL designs and MATLAB system models.
Integrate third-party VIPs for compliance testing of standard protocols such as Ethernet and PCIe
Take an active role in post-silicon chip bringup to help ensure a smooth transition to working silicon
Contribute to continuous improvement by developing forward looking automation and solutions. Enhance verification methodologies, processes, and infrastructure to improve scalability, productivity, and maintainability
Take opportunities to lead, plan, and coordinate tasks with team members

What You’ll Need

Proficiency in SystemVerilog and UVM, including developing and maintaining verification environments and testbenches
Experience applying constrained random verification methodologies to achieve thorough functional coverage
Experience verifying SerDes PHYs, DSPs, or analog mixed signal designs is preferred but not required
Knowledge in Ethernet and PCIe standards is desirable
Exposure to formal verification, gate level simulation, and power aware UPF verification techniques
Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

About You

Possess strong written and verbal communication skills and convey complex technical ideas clearly
Detail oriented and able to plan, prioritize, and manage multiple tasks effectively
Demonstrate a self motivated approach to problem solving and debugging issues
Comfortable taking ownership of projects and driving them to completion
Learn quickly and adapt well to evolving technologies and new challenges
Enjoy collaborating with peers and contributing to a team oriented work environment

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Pay range and Other Compensation & Benefits:

$108,000.00 - $158,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.

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More about this job

Responsibilities

The engineer will define, model, and verify high-performance ASIC IP blocks while collaborating with cross-functional teams to ensure design functionality. Responsibilities include developing testbenches, debugging simulations, and facilitating post-silicon chip bringup.

Requirements

Candidates must hold a degree in Science or Engineering with at least 1-2 years of relevant ASIC experience depending on the degree level. Proficiency in SystemVerilog and UVM is required, along with strong problem-solving and communication skills.

Skills

SystemVerilog
UVM
ASIC design
Verification
Validation
SerDes
Ethernet
PCIe
Python
Perl
C/C++
GNU Make
RTL
MATLAB
Mixed signal design
Debugging

Benefits

Annual discretionary bonus program
Annual RSU grants
Competitive benefits package

Visa sponsorship

Not detected in the job text

Keywords

ASIC
SystemVerilog
UVM
SerDes
PHY
DSP
Mixed Signal
Ethernet
PCIe
RTL
MATLAB
Python
Perl
C/C++
GNU Make
Verification
Validation
Integration
Post-silicon
UPF
Formal verification
Gate level simulation
Automation
Connectivity
Data centers
High performance
Low power
SoC
Compliance testing
Debugging

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