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Added 3 months ago
R
SMTS Logic Design
Rambus
Montreal, QC
- Other
Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work
Added 3 months ago
G
Analyste de données / Data Scientist
Genetec
Remote, Canada
- Full-time
- Remote
Maîtrise avancée de Python (Pandas, NumPy, Scikit-learn) et expérience dans l’utilisation de bibliothèques d’apprentissage automatique
Added 4 months ago
S
Architecte en IA agentique - Intelligence Engineering / Agentic AI - Sr. Architect - Intelligence Engineering
Slalom
Montreal, Quebec
- Full-time
Développer en Python et, lorsque pertinent, dans d’autres langages afin de livrer des systèmes d’apprentissage automatique, des API, des harnais d’évaluation, des pipelines de récupération,…
Added 4 months ago
S
Agentic AI Architect - Intelligence Engineering (Toronto)
Slalom
Toronto, Ontario · Greater Toronto Area, Canada
- Full-time
Build in Python and, where useful, other languages to deliver machine learning systems, APIs, evaluation harnesses, retrieval pipelines, agent workflows, and production services
Added 4 months ago
DC
Software QA - Intermediate (Cloud Platform)
Delta Controls
Surrey, British Columbia
- Full-time
Work Location: Hybrid (In-office 3 days per week, subject to change)
Added 4 months ago
DC
Software Developer - Cloud - Intermediate
Delta Controls
Surrey, British Columbia
- Full-time
Work Location: Hybrid (In-office 3 days per week, subject to change)
Added 3 months ago
PR
Senior Robotics Software Developer
Promise Robotics
Calgary, AB
- Full-time
We’re looking for a Senior Robotics Software Developer to join our team and contribute to developing cutting-edge solutions for our core robotic manufacturing technologies. This is a senior…
Added 1 month ago
F
Staff Software Engineer - Code Authoring
Forerunner
Kitchener, ON
- Full-time
…unmatched speed and quality. The Code Authoring team owns the developer environment at Faire: the AI coding tools engineers use every day, remote development environments, and the sandboxes…
Added 4 months ago
SC
Senior to Principal Geotechnical Engineer / Ingénieur(e) géotechnique – niveau sénior à principal(e)
SRK Consulting
Montreal, Quebec
- Full-time
Ability to work independently, onsite, outside and in remote locations.
Added 4 months ago
RB
Senior Analyst, Acquisition
Rogers Bank
Toronto, Ontario
- Full-time
Data analysis skills must include 2+ years of experience using statistical programs such as SAS, Python, R, Knowledge Studio, or similar
Added 3 months ago
PR
Robotics Software Developer
Promise Robotics
Calgary, AB
- Full-time
We’re looking for a Robotics Software Developer to join our team and contribute to developing cutting-edge solutions for our core robotic manufacturing technologies. This is an early-career…
Added 4 months ago
E
FPGA Design Engineer
Evertz
Burlington, Ontario
- Full-time
Scripting and automation using Python, Tcl, or similar for build, test, or validation flows
Added 4 months ago
E
Senior Software Engineer - Backend
Evertz
Burlington, Ontario
- Full-time
5+ years of software engineering experience in a strongly typed language; Java preferred (Python, Rust, Go, C++, or C# also considered)
Added 1 month ago
A
Test/Lab Engineer
Actalent
Oakville, ON
- Contract
Professional, co-op, or academic experience with Python development.
Added 4 months ago
ES
Senior Technical Artist - EA SPORTS FC
EA SPORTS
Vancouver, British Columbia
- Full-time
…leading edge content across multiple disciplines. This team works onsite in our Burnaby office 3…
Added 3 months ago
CC
Senior Product Engineer - Onsite Position
Curtiss-Wright Corporation
Ottawa, ON · Canada-Ottawa
- Full-time
- Scripting/automation experience (Python or similar)
Added 1 month ago
A
RF System Verification Engineer
Actalent
Sainte-Anne-de-Bellevue, QC
- Contract
Il s'agit d'un poste fully onsite, situé à Sainte-Anne-de-Bellevue,QC.
Added 1 month ago
PC
Sr. Data Engineer - Toronto, ON (Hybrid)
Pozent Corporation
Toronto, ON
- Contract
Skills - Must have
Added 4 months ago
E
Thanks for visiting our Job Board. Please review our open positions and apply to the positions that match your qualifications.
Evertz
Burlington, Ontario
- Full-time
Scripting and automation using Python, Tcl, or similar for build, test, or validation flows
Added 4 months ago
G
Spécialiste en tests logiciels / Software Test Specialist
Genetec
Montreal, Quebec
- Full-time
Connaissance de la programmation orientée objet et les langages de script (C#, F#, PowerShell, Python)
Added 2 months ago
I
Software Engineer II - Toronto
INSTALILY.AI
Toronto, ON
- $90,000 to $110,000 CAD / year
Strong fluency in at least one backend language (Python, TypeScript, or similar) and a modern web stack
Added 1 month ago
PC
Senior Automation Engineer - Toronto, ON (Hybrid)
Pozent Corporation
Toronto, ON
- Contract
Skills - Must Have
Added 1 month ago
EA
Senior Software Engineer - Generative Engine Tools
Electronic Arts (EA)
Vancouver, BC
- Full-time
This is a hybrid role, onsite three days a week, in Redwood City, Montreal, or Vancouver.
Added 1 month ago
EA
Senior Software Engineer - Backend
Electronic Arts (EA)
Vancouver, BC
- Full-time
This is a hybrid role, onsite three days a week, in Redwood City, Montreal, or Vancouver.
Added 1 month ago
RE
Tools Developer (Apex Legends)
Respawn Entertainment
Vancouver, BC · Greater Vancouver Metropolitan Area
- Full-time
create groundbreaking games with some of the best developer talent in the industry.

Rambus

SMTS Logic Design

450 Rue St-Pierre Street, Suite 300, Montreal, QC, H2Y 2M8, Canada

Apply on careers-rambus.icims.com About employer

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Job details

Apply by: Aug 3, 2027
Experience: 8+ years of ASIC/SoC logic design experience with proven delivery of complex silicon products from architecture through tape-out.
Posting language: English
Posted: Aug 3, 2026

Original job description

Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of Technical Staff (SMTS) – Logic Design Engineer to join our PCIe Switch Architecture and Design team in Montreal, Canada. In this role, you will be working with some of the brightest inventors and engineers in the world developing next-generation PCIe Gen6/Gen7 switch products that make data faster and safer.

As a Senior Member of Technical Staff (SMTS) – Logic Design Engineer, you’ll play a pivotal role in PCIe Gen6/Gen7 switch IP development, contributing to architecture definition, micro-architecture development, RTL implementation, and design closure of high-performance ASIC IP. In this full-time role, you’ll report directly to the Logic Design leadership team. Our PCIe Switch Architecture and Design team is dedicated to developing scalable, high-performance switch IP for advanced connectivity solutions, and your contributions will be instrumental in delivering next-generation PCIe switch product milestones.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities

The successful candidate will contribute across the full product lifecycle, from architecture and micro-architecture through RTL implementation, verification support, emulation, and design closure.

Analyze product requirements and contribute to architecture and micro-architecture development for next-generation PCIe Gen6/Gen7 switch products.
Define and document complex hardware subsystems, including PCIe switch fabric, port controllers, routing and arbitration logic, flow control and credit management, buffer management, power management features, and configuration/register infrastructure.
Review specifications and identify implementation risks, performance bottlenecks, scalability concerns, and opportunities for design optimization.
Develop high-quality, synthesizable RTL using SystemVerilog and design high-performance pipelines capable of supporting PCIe Gen6 and Gen7 data rates.
Implement timing-conscious and physically-aware architectures suitable for advanced process nodes, ensuring RTL is scalable, reusable, and maintainable.
Lead the development of significant design blocks independently and drive resolution of complex technical issues spanning architecture, implementation, and verification.
Mentor junior and intermediate engineers, participate in design reviews, and provide technical guidance across the team.
Collaborate with verification engineers to define verification strategies, coverage goals, and debug approaches.
Support block, subsystem, emulation, FPGA, and silicon debug activities, including analysis of protocol, performance, and functional issues discovered during verification or customer engagements.
Conduct RTL reviews, enforce coding guidelines, and support CDC, RDC, lint, synthesis, and timing closure activities.
Participate in continuous improvement of design methodologies, automation flows, and development processes.

Qualifications

Candidates should demonstrate strong ASIC/SoC logic design experience, technical leadership, and the ability to deliver complex silicon IP from architecture through tape-out.

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline.
8+ years of ASIC/SoC logic design experience with proven delivery of complex silicon products from architecture through tape-out.
Expert knowledge of SystemVerilog, RTL design methodologies, and ASIC development flows.
Strong understanding of pipelined architectures, resource arbitration, state machine design, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques.
Experience with synthesis and timing closure, including industry-standard EDA tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus, SpyGlass, and Questa/Visualizer.
Preferred: deep knowledge of PCIe Gen5/Gen6/Gen7 protocol architecture and experience designing PCIe switches, root complexes, PCIe endpoints, or high-speed interconnect fabrics.
Preferred: familiarity with CXL, PTM, ATS/PASID/PRI, SR-IOV, and PCIe power management features.
Preferred: experience with emulation platforms such as HAPS, Palladium, or Veloce, and experience with performance modeling or architectural simulation in Python or C++.
Strong problem-solving, analytical, communication, documentation, mentoring, and technical leadership skills, with the ability to work effectively across architecture, verification, software, and customer-facing teams.

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Apply on careers-rambus.icims.com About employer

More about this job

Responsibilities

The candidate will contribute to the full product lifecycle of PCIe Gen6/Gen7 switch IP, including architecture definition, RTL implementation, and design closure. They will also mentor junior engineers and collaborate with verification teams to ensure high-performance silicon delivery.

Requirements

Candidates must have 8+ years of ASIC/SoC logic design experience and a degree in Electrical or Computer Engineering. Expert knowledge of SystemVerilog, RTL methodologies, and industry-standard EDA tools is required for this role.

Skills

Logic Design
PCIe Gen6/Gen7
SystemVerilog
RTL Implementation
ASIC/SoC Design
Timing Closure
Synthesis
Pipelined Architectures
Clock-domain crossing
Reset-domain crossing
Low-power design
Technical leadership
Verification support
Emulation
Silicon debug

Benefits

Bonus
Equity
Employee benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC
SoC
Logic Design
PCIe
SystemVerilog
RTL
Synthesis
Timing Closure
Synopsys Design Compiler
Cadence Genus
SpyGlass
CXL
Emulation
HAPS
Palladium
Veloce
Silicon IP
Data Center Connectivity
Semiconductor
Architecture
Micro-architecture
CDC
RDC
Python
C++
SR-IOV
High-speed interconnect

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Work requirements

Jobs in Canada