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Added 4 hours ago
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Senior Forward Deployed Engineer
Didero
Toronto, ON
- Full-time
We are looking for a Senior Forward Deployed Engineer to join our team. This role is ideal for a technically strong, customer-facing engineer who can understand complex customer operations,…
Added 4 hours ago
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Security Engineer, Vulnerability Management
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- Full-time
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RV
Senior Hardware Engineer-Platforms
Ross Video
Ottawa, ON · Nepean, ON
- Full-time
The ideal candidate is a pragmatic hardware systems engineer who understands how FPGA logic, PCB construction, signal integrity, power distribution, clocks, firmware, thermal behavior, and…
Added 5 hours ago
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Staff Site Reliability Engineer, Application
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Toronto, ON
- Full-time
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Toronto, ON
- Full-time
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- Full-time
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Forward Deployed Engineer
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Toronto, ON
- $90,000 to $130,000 CAD / year
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Toronto, ON
- $35 to $40 CAD / hour
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GTM Engineer
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- Full-time
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AI Product Engineer
Angel Host
Montreal, QC
- Full-time
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Added 7 hours ago
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AI Product Engineer IT - Montréal, Quebec (Hybrid)
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Montreal, QC
- Full-time
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- Full-time
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Application Engineer/Technologist
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Senior Site Reliability Engineer
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Senior Windows Server Automation Engineer
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Senior Electrical Engineer A
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Ross Video

Senior Hardware Engineer-Platforms

Ottawa, ON, Canada
Nepean, ON, Canada

The pay range for this role in Canada is: $122,500-$160,000 CAD · Full-time

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Job details

Pay: The pay range for this role in Canada is: $122,500-$160,000 CAD
Job type: Full-time
Apply by: Dec 5, 2026
Posting language: English
Posted: Nov 5, 2026

Original job description

Date Posted: Nov 5, 2026

Preferred Location: Nepean, ON, Canada

Alternate Location(s): Not Available

Internal Requisition ID: 2027-002

Requisition Type: Replacement Position

Remote Type: Hybrid Remote

On Call Required: No

Travel Required: No

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Description

Why You’ll Love Working at Ross Video:

At Ross Video, you’ll be part of a team energized by innovation, building the cutting-edge technology that powers the world’s most watched live productions and events. Our products are designed to be intuitive, reliable, and to deliver exceptional results - because our customers’ success is everything to us. If you’ve ever watched live television, breaking news, major sports, or a Hollywood award show, you’ve seen our technology in action. Join us behind the scenes and help make unforgettable live moments possible.

THE OPPORTUNITY

Join the Hyperconverged Solutions R&D team developing the FPGA, SoC, embedded-control, and high-speed hardware platforms that power professional live video production.

This is a hands-on, on-site engineering role focused on system-level signal integrity, FPGA and SerDes bring-up, and practical hardware problem-solving. You will work directly with prototype hardware, lab equipment, FPGA tools, embedded software, PCB designers, and cross-functional engineering teams to bring complex products from architecture through production.

The ideal candidate is a pragmatic hardware systems engineer who understands how FPGA logic, PCB construction, signal integrity, power distribution, clocks, firmware, thermal behavior, and manufacturing interact. This position is expected to be primarily performed from the office and is not designed as a mostly work-from-home role.

What You Will Do

Own or contribute to the architecture, design, implementation, bring-up, and sustaining support of FPGA-based hardware platforms.
Develop and review requirements, component selections, schematics, FPGA partitioning, interface definitions, timing budgets, and technical risk assessments.
Own or contribute to system-level signal-integrity analysis across the complete channel, including FPGA transceiver, package and pin breakout, connector, PCB, backplane, cable, and receiving device.
Develop and review channel models, stackups, routing constraints, loss budgets, crosstalk assumptions, timing margins, and SI simulation results using HyperLynx or equivalent tools.
Design and debug FPGA, SoC, CPLD, and embedded-control functions using SystemVerilog, Verilog, VHDL, C/C++, Python, Tcl, or shell scripting as appropriate.
Work with PCB designers on high-density, high-speed boards, including component placement, transceiver breakouts, stackups, fabrication constraints, power distribution, thermal considerations, and design-for-manufacture.
Bring up and validate high-speed SerDes links using oscilloscopes, BERT/JBERT equipment, vendor tools, eye diagrams, bathtub curves, BER testing, and structured margining.
Configure and tune FPGA transceiver PMA and PCS parameters, including transmitter emphasis and equalization, receiver equalization, CTLE/DFE settings where applicable, output swing, polarity, clocking, reference clocks, lane alignment, and calibration behavior.
Develop transceiver initialization, calibration, monitoring, and diagnostic flows that work across board revisions, temperature, voltage, manufacturing variation, and production units.
Correlate simulation, FPGA transceiver settings, power behavior, and laboratory measurements to drive links to reliable operation.
Determine whether failures originate in FPGA configuration, transceiver settings, reference clock, power integrity, PCB channel, connector, backplane, firmware, or the test setup.
Write and debug low-level software, scripts, diagnostics, and register-access tools used for bring-up, testing, transceiver configuration, and production support.
Support timing closure, CDC and reset analysis, implementation constraints, resource optimization, and FPGA debug.
Participate in design reviews, validation planning, ECOs, board revisions, production transfer, RMA investigations, and field-return analysis.
Collaborate with PCB, mechanical, software, verification, product validation, manufacturing, product management, and customer-support teams.
Create clear architecture, design, bring-up, test, and troubleshooting documentation.
Mentor less-experienced engineers and contribute reusable test methods, automation, diagnostics, and design practices.

Technical Environment

Large routed platforms, processing blades, FPGA/SoC subsystems, I/O systems, PCIe and Ethernet backbones, crosspoint logic, and embedded control
System-level SI and PI analysis, high-density PCB construction, stackup selection, high-speed routing, transceiver breakouts, timing budgets, and design-for-manufacture
AMD and Intel FPGA/SoC devices, integrated transceivers, vendor IP, timing analysis, on-chip debug, PMA/PCS configuration, calibration, and margin testing
SMPTE SDI, proprietary video interfaces, AES/MADI audio, Ethernet, PCIe, DDR3/DDR4/DDR5, source-synchronous buses, clocks, PLLs, and reset architectures
Prototype bring-up, production readiness, manufacturing support, ECOs, board revisions, sustaining engineering, and field-return investigation

What We Are Looking For Required Qualifications

Several years of hands-on experience developing complex FPGA-based hardware or embedded hardware systems.
Willingness and ability to work primarily from the office and spend substantial time in the lab.
Demonstrated ability to physically debug hardware, including soldering, rework, probing, and using laboratory instrumentation.
Strong system-level understanding of the interactions among FPGA logic, PCB design, power, clocks, resets, firmware, SI/PI, thermal behavior, and manufacturing constraints.
Demonstrated experience with system-level signal integrity on high-speed digital hardware.
Practical experience performing or interpreting SI simulations using HyperLynx or an equivalent tool.
Practical experience with PCB stackups, high-speed channel construction, transceiver breakouts, connectors, backplanes, and loss/crosstalk tradeoffs.
Hands-on experience bringing up and tuning FPGA or ASIC SerDes transceivers.
Understanding of PMA/PCS architecture, transmitter and receiver equalization, calibration, reference clocks, lane alignment, initialization, eye measurements, and BER or margin testing.
Experience with SystemVerilog, Verilog, or VHDL.
Experience with schematic capture and PCB design-review processes.
Experience with high-speed interfaces such as SDI, Ethernet, PCIe, serial transceivers, DDR, or comparable technologies.
Experience diagnosing hardware failures through structured experiments, measurements, simulation, and root-cause analysis.
Ability to communicate technical decisions clearly and work effectively across engineering disciplines.

Strongly Preferred

AMD and/or Intel FPGA development experience, including timing closure, vendor IP, transceiver configuration, calibration, and on-chip debug.
Experience with power-distribution networks, decoupling, power sequencing, monitoring, and power-integrity analysis.
Embedded C/C++, Linux or RTOS-based systems, Python, Tcl, or shell scripting.
Experience with PCIe-to-Ethernet architectures or low-level hardware-control software.
Professional broadcast-video experience, particularly routing, distribution, multiviewer, or hyperconverged production systems.
Experience using AI-assisted engineering tools with appropriate technical review and validation.

Working Style

We value engineers who are technically curious, direct, and practical. You should be comfortable making decisions with incomplete information, testing assumptions in the lab, and changing direction when the evidence says the original theory was wrong. The strongest candidates will be able to explain both the underlying electrical or FPGA principles and the practical steps they took to make a product work reliably.

What Success Looks Like

High-speed links are brought up methodically and achieve reliable operation with documented margin.
SI and PI risks are identified early and connected to practical design, layout, and validation decisions.
Prototype and field failures are resolved through evidence-based root-cause analysis rather than speculation.
Designs are practical, reviewable, testable, maintainable, and production-ready.
Cross-functional teams receive useful technical direction, timely support, and clear documentation.
The engineer becomes a trusted owner of significant subsystems and contributes to the reliability and maintainability of the overall platform.

Level and Growth

This is a Senior Engineer role with meaningful subsystem and platform responsibility. The successful candidate may grow into Principal-level scope by demonstrating sustained architectural ownership, technical leadership, cross-functional influence, and the ability to elevate the broader engineering team.

What We Offer:

Ross provides competitive compensation, comprehensive benefits, and the flexibility you need to do your best work, including flexible hours, generous paid time off, and a wellness allowance. You’ll also have the opportunity to share in our success through our employee share ownership program and grow your career with ongoing learning and development support. We value connection and collaboration, with plenty of events and opportunities to build relationships across the company. Most importantly, you’ll be part of a team that’s passionate about what we do and how we do it.

Salary Information:

The pay range for this role in Canada is: $122,500-$160,000 CAD

The listed salary reflects the pay range for a role based in Canada. Compensation may differ based on alternate locations if listed. Final compensation will be determined by location, skills, experience, knowledge, and role-specific qualifications, and may be adjusted to recognize candidates accordingly. If your experience or compensation expectations differ from the posted range, we still welcome your application.

Use of Artificial Intelligence in Hiring

Ross uses a secure, closed AI system to support recruitment. Your information is protected and used only to help us efficiently identify qualified candidates. We encourage all applicants to apply, even if you do not meet every requirement - if you bring relevant skills, enthusiasm and a willingness to learn, we want to hear from you.

Our Commitment to Fostering an Inclusive Environment

We want you to bring your authentic self to work, regardless of race, color, religion, sexual orientation, gender, gender identity or expression, marital status, age, veteran status, physical or mental disability. Inclusivity drives innovation and creativity, and that’s something we’re passionate about!

If you require accommodations throughout any stage of the recruitment, assessment, and selection process, please contact our Talent Acquisition team at [email protected] , and we will make all reasonable efforts to accommodate your request.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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More about this job

Responsibilities

Design, bring up, validate, and sustain FPGA-based hardware platforms, including high-speed SerDes links, while analyzing signal integrity and resolving system-level hardware issues. Collaborate across engineering and manufacturing teams on architecture, PCB design, testing, production readiness, documentation, and technical mentorship.

Requirements

Candidates need several years of hands-on experience with complex FPGA or embedded hardware, high-speed signal integrity, SerDes transceivers, PCB design reviews, and physical lab debugging. They should be proficient in an HDL and able to diagnose failures through structured measurements, simulation, and root-cause analysis; AMD or Intel FPGA experience and embedded software skills are preferred.

Skills

FPGA Hardware Design
System-Level Signal Integrity
SerDes Bring-Up and Tuning
PCB Design Review
High-Speed Channel Modeling
SI Simulation
SystemVerilog
Verilog
VHDL
Embedded C/C++
Python Scripting
FPGA Timing Closure
Power Integrity
Hardware Debugging
Root-Cause Analysis
Laboratory Instrumentation

Benefits

Comprehensive Benefits
Flexible Hours
Paid Time Off
Wellness Allowance
Employee Share Ownership Program
Learning and Development Support
Company Events

Visa sponsorship

Not detected in the job text

Keywords

FPGA
SoC
CPLD
SerDes
Signal Integrity
Power Integrity
HyperLynx
SystemVerilog
Verilog
VHDL
C/C++
Python
Tcl
Linux
RTOS
PCIe
Ethernet
SMPTE SDI
DDR3/DDR4/DDR5
PMA/PCS
BERT/JBERT
Eye Diagrams
BER Testing
Timing Closure
Clock and Reset Architectures
PCB Stackups
High-Speed Routing
Power Distribution Networks
Design for Manufacture
Hardware Bring-Up

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