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Schweitzer Engineering Laboratories (SEL)

Lead RTL Engineer

Burnaby, BC, Canada
Canada - Burnaby, Canada

$105,600 to $158,400 CAD / year · Full-time

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Job details

Pay: $105,600 to $158,400 CAD / year
Job type: Full-time
Posting language: English
Posted: Oct 9, 2026

Original job description

Schweitzer Engineering Laboratories (SEL) is hiring a Lead Engineer with a focus in VHDL Register-Transfer Level (RTL) Digital Logic design for our R&D Communications product group. In this role, you will develop and support our SONET/VSN Multiplexer with TDM interfaces, Ethernet Circuit Emulation Gateway, Satellite Synchronized Network Clocks, Ethernet Switches, and other communication products.

A typical day as a Lead VHDL RTL Digital Logic Engineer might include:

Serving as technical lead on complex VHDL RTL digital logic projects.
Creating and maintaining internal RTL design documentation.
Writing test plans and developing test harnesses/stimulus for RTL functional verification.
Preparing design and system level specifications.
Participating or moderating peer reviews of designs, documentation and test plans.
Providing and maintaining accurate project plans and labor estimates.
Working closely with product managers on new product concepts and enhancements.
Engaging with cross-discipline teams to deliver world-class products for critical infrastructure.
(3-5 essential duties and responsibilities of the job that paint a picture of what someone in this role would regularly do)

This job might be for you if:

are passionate about designing RTL digital logic for FPGAs.
enjoy solving difficult problems with efficient and creative solutions.
have experience in both RTL, hardware and firmware development practices.
are knowledgeable in networking protocols, Ethernet (IEEE 802.3), MPLS, SONET and precise timing technologies such as PTP (IEEE 1588), IRIG-B and GPS.
want a career making electric power safer, more reliable, and more economical.

Required Qualifications:

B.S. degree in Electrical Engineering, related discipline, or equivalent combination of education and experience
5+ years of combined experience in the following areas:
- RTL Digital Design with FPGAs using VHDL/Verilog
- Xilinx, Intel FPGA (Altera), Microchip (Microsemi/Actel), Lattice Semiconductor Tools
- Firmware Design with FPGA SOCs/Microprocessors using C/C++
- Simulation, Synthesis and Timing Analysis of Digital Logic
- Functional verification of RTL Digital Logic
Ability to work cooperatively in a team environment
Ability to rapidly learn new skills and assume new responsibilities
Ability to mentor others
Strong writing, technical documentation and speaking
Background check results satisfactory to SEL
Negative drug test result(s)

It is a plus if you have:

Supervisory experience or training
JIRA development process (DCP, Closeout, Standups, Sprints), GITHUB, Confluence

About Schweitzer Engineering Laboratories:

SEL designs, manufactures, and supports products and systems that protect, monitor, control, and automate electric power systems. Our technologies help detect faults, prevent equipment damage, and reduce the impact of power outages.

Our mission is to make electric power safer, more reliable, and more economical. Employees contribute to practical, high-quality solutions used every day, where attention to detail and quality directly support the reliability of the electric grid.

Location - Burnaby, BC

Burnaby, BC – This position is located in Burnaby, BC, east of Vancouver. Burnaby is the one of the largest cities in British Columbia. Burnaby has designated 25% of their land to parks and open spaces, making it ideal for those looking for that big city feel and maintaining the comfort of open spaces.

Competitive pay. Superior benefits. Inspiring work.

People are at the core of our company. We welcome you to learn more about how we support employees.

SEL makes an annual Registered Retirement Savings Plan (RRSP) contribution for eligible employees. The group RRSP also supports personal contributions.
We offer top tier health insurance that includes extended coverage for medical, prescription, dental, vision, life, and disability insurance.
We recognize the importance of a healthy life balance and offer: Statutory paid holidays, personal holidays, annual vacation accrual starting at 15 days, 9 paid sick days, parental leave that covers up to 90% of regular earnings, and family medical and compassionate leave.
We foster growth and development of our employees through avenues such as apprenticeships, tuition assistance, and engineering development programs.
Ask our team about other benefits including wellness, and adoption assistance.

Pay Range Data: $105,600 - $158,400 CAD annually

We set starting pay based on job-related factors such as your experience, training, knowledge, and skills. We are looking to fill this position at the Lead Engineer level, and we welcome applicants with a range of experience. Depending on your background, we may consider you for a different level, with compensation aligned accordingly.

Communication with Applicants

We communicate with all applicants. If you do not receive a response about your application, please check your SPAM filter or reach out to us at careers@selinc.com.

SEL is an Equal Opportunity Employer: Vets/Disabled.

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More about this job

Responsibilities

The Lead RTL Engineer will serve as the technical lead for complex digital logic projects and develop test plans for functional verification. They will also collaborate with cross-discipline teams and product managers to deliver high-quality communication products for critical infrastructure.

Requirements

Candidates must hold a Bachelor's degree in Electrical Engineering or a related field and possess at least 5 years of experience in RTL digital design with FPGAs. Proficiency in VHDL/Verilog, firmware development, and knowledge of networking protocols are essential for this role.

Skills

VHDL
RTL design
Digital logic
FPGA
Verilog
C
C++
Ethernet
Networking protocols
Functional verification
Timing analysis
Synthesis
Technical documentation
Project planning
Mentoring
Hardware development

Benefits

Health insurance
Dental insurance
Vision insurance
Life insurance
Disability insurance
Paid holidays
Paid sick days
Annual vacation
Parental leave
Family medical leave
Compassionate leave
Tuition assistance
Engineering development programs

Visa sponsorship

Not detected in the job text

Keywords

VHDL
RTL
FPGA
Digital Logic
Verilog
Xilinx
Intel FPGA
Microchip
Lattice Semiconductor
Firmware
C
C++
Ethernet
MPLS
SONET
PTP
IEEE 1588
IRIG-B
GPS
JIRA
GITHUB
Confluence
Electrical Engineering
Verification
Synthesis
Timing Analysis
Communications
Infrastructure
Product Development
Technical Leadership

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