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ShawSilicon

Senior FPGA Design Engineer, RTL to Timing Closure

  • Toronto, ON, Canada

Full-time

This opening has closed.

The original listing is kept below for reference.

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Job details

Job type
Full-time
Closing date
Posting language
English
Posted

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Original job description

Archived listing. The details below describe a past opening.

USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB, or APB integrationLow power design intent (UPF)Own the link, not just the RTL - this role targets engineers who have taken high-speed int…SystemVerilogPCIe/CXLAXI/AMBACDCDDR4Timing closureShip inference datapaths - this role targets engineers who understand the workload, not ju…SystemVerilogRTL DesignFixed-pointAMBA AXISynthesisTiming closureOwn testbench architecture end to end - this role targets engineers who build verification…UVMSystemVerilogSVAAMBA/AXICoverage ClosurePython/TCL
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Responsibilities

Design and implement FPGA and RTL solutions, including high-speed interfaces and inference datapaths, and drive designs through synthesis and timing closure. Own verification architecture and testbench development, including assertions, constrained-random testing, and coverage closure.

Requirements

The role calls for senior-level experience in SystemVerilog or VHDL RTL design, FPGA implementation, and timing closure. Relevant expertise includes UVM-based verification, CDC and lint signoff, synthesis and static timing tools, AMBA interfaces, and high-speed protocols such as PCIe, CXL, DDR, or Ethernet.

Skills

  • SystemVerilog
  • RTL Design
  • FPGA Design
  • Timing Closure
  • UVM
  • Functional and Code Coverage
  • SystemVerilog Assertions
  • Constrained-Random Verification
  • Vivado
  • Quartus
  • Clock Domain Crossing
  • PCIe
  • Ethernet
  • DDR
  • AMBA AXI
  • Static Timing Analysis

Visa sponsorship

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Categories

  • Engineering
  • Technology
  • Manufacturing

Keywords

  • SystemVerilog
  • VHDL
  • FPGA
  • RTL Design
  • UVM
  • SystemVerilog Assertions
  • Constrained-Random Verification
  • Functional Coverage
  • Code Coverage
  • VCS
  • Xcelium
  • Questa
  • Vivado
  • Quartus
  • Timing Closure
  • SDC
  • XDC
  • Clock Domain Crossing
  • PCIe
  • CXL
  • Ethernet
  • DDR4
  • On-Chip Debug
  • ILA
  • Signal Tap
  • SpyGlass
  • Design Compiler
  • Genus
  • AMBA
  • AXI

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