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Stefanini North America and APAC

FPGA Design Engineer

Ottawa, ON, Canada
Kanata, ON, Canada

Job type: Contract
Apply by: Oct 30, 2026
Posting language: English
Posted: Sep 30, 2026

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Applications open in a new tab.

Original job description

Details:

Stefanini Group is hiring!

Stefanini is looking for FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa, Ontario, Canada

For quick apply, please contact Prakhar Goel Ph: 248 263 5255/

[email protected]

22 Total Days PTO (See Below the breakdown)

10 Days Time-off (80 Hours of Time-Off- Accrual Basis)
9 Holidays on average throughout the year
3 Personal Days

IMP: Digital Signal Processing (DSP) is a must have skill for the role.

Ideal Candidate: FPGA designer engineer with Radio experience. Working with 4G/5G Radios. 7+ years of experience Heavy System Verilog and RTL experience.

They DO NOT USE VHDL.

Tools: Altera Quartus. Matlab/Simulink for modeling Axi and Ethernet protocol experience are more important than other high-speed experience.

Responsibilities:

Works on unusually complex problems and provides highly innovative solutions Uses independent judgment to accomplish goals and objectives
Has insight into industry trends and communicates vision to guide organizational strategy and long-range planning
Lends research and contributes to evaluations, project plans and budgets for new products or updates existing products
Acts as consultant on critical projects that impact long term organizational goals and objectives
Leads teams, gives technical guidance and communicates with senior management on progress Identifies or creates solutions that are likely to contribute to the development of new company concepts
Expected to set standards and achieve cost targets for product cost through proper design choices, component selection or supplier selection
Demonstrated expertise in competitive analysis
May actively seek customer input and take responsibility for internal and external customer situations
Determines requirements and functional specifications for entire system, under only consultative direction.

Job Requirements

Details:

What You'll Do:

Design & Architecture:

Develop FPGA IP architecture for 4G/5G Radio Units.
Contribute to system-level design aligned with 3GPP and O-RAN Alliance specifications.
Implementation:
Implement complex RTL blocks (Verilog/SystemVerilog) and integrate into larger systems.
Optimize FPGA resource utilization and ensure timing closure.

Validation & Testing:

Define and execute verification plans using UVM and advanced techniques.
Perform simulation and system-level FPGA validation.

Collaboration:

Work closely with Radio Unit development teams for seamless integration.
Partner with software teams to ensure hardware-software interoperability.
Mentor junior engineers and participate in technical reviews.

What You'll Bring

Essential Requirements:

Proven experience in FPGA design and RTL development.
Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing. This is a specialized subset of Digital Signal Processing (DSP) specifically focused on telecommunications and wireless fronthaul/baseband engineering.
Familiarity with JESD204B/C, Ethernet, PCIe, AXI, and high-speed SERDES.
Tools: Quartus, Vivado, MATLAB/Simulink, HDL Coder.
Knowledge of UVM and verification methodologies.
Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.
Experience with Git/GitHub and version control workflows.

Desirable Skills:

7+ years of FPGA design experience in wireless or high-speed systems.
Experience in high-volume wireless products and IP development.
Contributions to standards bodies or technical forums (O-RAN, 3GPP).

Stefanini takes pride in hiring top talent and developing relationships with our future employees. Our talent acquisition teams will never make an offer of employment without having a phone conversation with you. Those face-to-face conversations will involve a description of the job for which you have applied. We also speak with you about the process including interviews and job offers.

About Stefanini Group:

The Stefanini Group is a global provider of offshore, onshore and near shore outsourcing, IT digital consulting, systems integration, application, and strategic staffing services to Fortune 1000 enterprises around the world. Our presence is in countries like the Americas, Europe, Africa, and Asia, and more than four hundred clients across a broad spectrum of markets, including financial services, manufacturing, telecommunications, chemical services, technology, public sector, and utilities. Stefanini is a CMM level 5, IT consulting company with a global presence. We are CMM Level 5 company

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More about this job

Responsibilities

Design FPGA IP architecture and implement complex RTL for 4G/5G radio units, optimizing resource use and achieving timing closure while aligning with 3GPP and O-RAN specifications. Lead verification and system-level validation, collaborate across radio and software teams, mentor engineers, and provide technical guidance on complex projects.

Requirements

Requires proven FPGA and RTL design experience, specialized telecommunications DSP knowledge, and familiarity with 4G/5G radio architecture, relevant protocols, and FPGA tools. The ideal candidate has 7+ years of wireless or high-speed systems experience, strong SystemVerilog skills, and knowledge of UVM and hardware-software integration.

Skills

FPGA Design
Digital Signal Processing
SystemVerilog
RTL Development
4G/5G Radio Systems
Verilog
Altera Quartus
MATLAB/Simulink
UVM Verification
NR/LTE Protocols
eCPRI/CPRI
PTP
Ethernet
AXI
JESD204B/C
PCIe

Benefits

Paid Time Off
Holidays
Personal Days

Visa sponsorship

Not detected in the job text

Hiring contact

Prakhar Goel

Keywords

FPGA
Digital Signal Processing
SystemVerilog
RTL
Verilog
4G
5G
Radio Units
3GPP
O-RAN
NR/LTE
eCPRI
CPRI
PTP
JESD204B/C
Ethernet
PCIe
AXI
SERDES
Altera Quartus
Vivado
MATLAB
Simulink
HDL Coder
UVM
FPGA Validation
Timing Closure
Git
GitHub
High-Speed Systems

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