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Added 52 mins ago
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Intermediate Data Engineer
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Toronto, ON
- $80 to $90 CAD / hour
- Contract
We are seeking a Data Engineer with experience in data engineering, cloud technologies, and machine learning operations to support the development and improvement of data capabilities.
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Miratech
Toronto, ON
- Full-time
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- Contract
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- Full-time
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Added 11 hours ago
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- Full-time
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Synopsys Inc

ASIC Physical Design, Sr Staff Engineer - 16724

Ottawa, ON, Canada
Nepean, ON, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Jan 4, 2027
Experience: 9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
Posting language: English
Posted: Sep 29, 2026

Original job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced ASIC Physical Design Engineer with a passion for innovation and a proven track record in complex SoC and test chip implementations. You thrive in collaborative environments, excel at cross-functional teamwork, and are ready to lead technical execution on advanced process nodes. Your expertise in the physical design flow and familiarity with industry-leading tools make you a valuable contributor to our mission of delivering robust, silicon-proven IP solutions.

What You’ll Be Doing:

Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
Driving tool flow automation and debugging to enhance productivity and design reliability.
Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.
Preparing and releasing all supporting views and documentation necessary for tape-out, maintaining mask tooling forms and checklists on foundry portals.

The Impact You Will Have:

Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

What You’ll Need:

9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
Familiarity with IP integration, test chip methodology, and advanced verification flows.
Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
Experience coordinating complex, cross-functional projects and leading technical execution.
Authorization to work in the USA.

Who You Are:

Analytical thinker with strong problem-solving skills and attention to detail.
Effective communicator, able to articulate complex technical concepts to diverse stakeholders.
Collaborative team player, fostering a culture of inclusion and innovation.
Proactive leader, driving continuous improvement and embracing new technologies.
Adaptable and resilient, thriving in fast-paced, dynamic environments.
Committed to excellence and quality in every aspect of design and delivery.

The Team You’ll Be A Part Of:

You’ll join the Test Chip PHY development team within Synopsys’s Silicon IP business. This group is dedicated to integrating and validating Synopsys’s broad portfolio of IP blocks - logic, memory, interfaces, analog, security, and embedded processors - into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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More about this job

Responsibilities

Implement and optimize physical design for test chips spanning DDR, HBM, and UCIe, from RTL through final GDS release, including floorplanning, power and ground planning, timing closure, and physical verification. Integrate IP and hard macros, automate and debug design flows, coordinate cross-functional execution, and prepare tape-out views and documentation.

Requirements

Requires 9+ years of ASIC physical design experience, including complex SoC or test chip implementations at advanced process nodes and expertise across the complete physical design flow. Candidates should be familiar with IP integration and advanced verification, proficient with industry CAD tools and FinFET technologies, able to lead cross-functional technical work, and authorized to work in the USA.

Skills

ASIC Physical Design
Floorplanning
Synthesis
Place And Route
Timing Closure
Static Timing Analysis
IR-Drop And Electromigration Analysis
Physical Verification
RTL-To-GDSII Flow
IP Integration
Test Chip Implementation
Design Compiler
PrimeTime
IC Compiler II
Fusion Compiler
IC Validator

Benefits

Health Benefits
Wellness Benefits
Financial Benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC Physical Design
SoC
Test Chips
DDR
HBM
UCIe
RTL
GDSII
Floorplanning
Power And Ground Planning
Synthesis
Place And Route
Timing Closure
Static Timing Analysis
IR-Drop
Electromigration
ERC
DRC
LVS
PERC
ESD Analysis
IP Integration
Hard Macros
Tape-Out
Design Compiler
PrimeTime
IC Compiler II
Fusion Compiler
IC Validator
Calibre

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