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Added 3 mins ago
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Synopsys Inc

Hardware Engineering, Staff Engineer- 19028

Ottawa, ON, Canada
Nepean, ON, Canada

Full-time

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Job details

Job type: Full-time
Apply by: Nov 29, 2026
Posting language: English
Posted: Oct 30, 2026

Original job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

A seasoned engineer with experience in DDR/HBM SIPI engineering. You possess a deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling. Your expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis, is unmatched.

You are proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS. You excel at generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers. Your knowledge in board-level construction and on-chip IO design operation allows you to work seamlessly across multi-site teams, communicating ideas, understanding problems, and finding solutions to create leading-edge designs.

As a team player, you communicate clearly and efficiently, leading issues to full closure independently. Your ability to track industry developments through activities at standards committees and memory vendor roadmaps ensures that you stay ahead of the curve in technological advancements.

What You’ll Be Doing:

Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.
Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.
Assess power delivery systems to optimize power integrity for supply stability and jitter minimization.
Document findings in reports and design guidelines.
Communicate results and insights to design teams to improve PHY design.
Communicate results and recommendations to customers to enable them to optimize their system performance.
Interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems.
Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.
Track industry developments through activities at standards committees and through memory vendor roadmaps.

What You’ll Need:

Proven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
Well-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
Ability to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.
Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
Knowledgeable in board-level construction and on-chip IO design operation.

The Impact You Will Have:

Enhance the performance and reliability of high-speed interface designs.
Drive improvements in system performance optimization techniques, contributing to lower power consumption and higher data rates.
Optimize power delivery systems, ensuring supply stability and minimized jitter.
Provide critical insights and recommendations that will shape the design and development of PHY components.
Enable customers to achieve optimal system performance through your expert guidance.
Contribute to the advancement of SIPI methodologies and their adoption by customers.
Help refine strategies to address signal and power integrity challenges in cutting-edge technologies.
Influence the direction of Synopsys’ DDR and HBM PHY roadmap.
Stay at the forefront of industry developments, ensuring Synopsys remains a leader in technological innovation.

Who You Are:

A team player able to communicate clearly and efficiently.
Ability to independently lead issues to full closure.

The Team You’ll Be A Part Of:

The R&D circuits team is tasked with providing SIPI solutions for the future DDR/HBM topologies and protocols, identifying key enablers, and providing support to early adopters or critical customers. We are also responsible for SIPI methodologies to be adopted by the customers and interconnect budgeting. ...Less

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More about this job

Responsibilities

Assess interconnects, signal margins, equalization strategies, and power delivery systems to improve DDR/HBM PHY performance, data rates, power efficiency, and reliability. Document and communicate analysis findings and recommendations to design teams and customers, while shaping PHY strategies and tracking industry developments.

Requirements

Requires strong expertise in high-speed interface signaling and signal and power integrity analysis, including statistical eye modeling, impedance matching, and resonant system analysis. Candidates should be proficient with HFSS/Ansys, HSPICE, Raptor, and ADS, understand board-level construction and on-chip I/O design, and communicate effectively while independently driving issues to closure.

Skills

DDR/HBM Signal and Power Integrity
High-Speed Interface Signaling
S-Parameter Analysis
Channel Loss and Crosstalk Analysis
Equalization Techniques
Jitter Analysis
Power Delivery Modeling
Statistical Eye Diagram Modeling
Return Loss and Impedance Matching
Resonant System Analysis
HFSS and Ansys Tools
HSPICE
Raptor
ADS
Board-Level Construction
On-Chip I/O Design

Visa sponsorship

Not detected in the job text

Keywords

DDR
HBM
SIPI
Signal Integrity
Power Integrity
High-Speed Interfaces
S-Parameters
Channel Loss
Crosstalk
Equalization
FFE
DFE
CTLE
Jitter
Power Delivery Modeling
Statistical Eye Diagram Modeling
Return Loss
Impedance Matching
Resonant System Analysis
HFSS
Ansys
HSPICE
Raptor
ADS
PHY Design
Interconnect Budgeting
Board-Level Construction
On-Chip I/O Design
Memory Vendor Roadmaps
Standards Committees

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