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Added 10 mins ago
AMS Design Verification Engineer
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Mississauga, ON
You push back when a test plan is too shallow or a coverage metric does not actually prove what it claims to prove, and you do it constructively
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Synopsys

AMS Design Verification Engineer

Mississauga, ON, Canada

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Job details

Posting language: English
Posted: Oct 16, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You understand that the real challenge in mixed-signal verification is not running simulations, it is building environments where analog and digital worlds talk to each other without breaking. You have spent time in the space between RTL and transistor-level netlists, where a single timing mismatch or convergence issue can derail a week of work, and you have learned how to catch those issues before they cascade.

You are comfortable reading a schematic, understanding such as ADC, AFE, PLL is supposed to do, and then building the test bench that proves it does it under every corner case that matters. Debugging does not intimidate you. You think of coverage and corner cases.

What You'll Be Doing

Define and execute verification test plans for Ethernet and PCIe SERDES IP, tracking coverage metrics and ensuring completeness across functional, analog, and mixed-signal scenarios
Build and maintain UVM-based SystemVerilog testbenches integrated with AMS co-simulation flows, combining RTL, behavioral models, and transistor-level netlists into unified verification platforms
Verify SERDES subsystems including TX/RX datapaths, equalization algorithms, CDR loops, PLL locking behavior, and analog-digital interface interactions across process corners and operating conditions
Debug simulation failures that span analog, digital, and mixed-signal domains using tools like HSPICE, XA, CustomSim, and VCS
Perform design reliability checks including electromigration, IR drop analysis, and device-level stress evaluations to ensure robustness in production silicon
Collaborate with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to align verification strategies with IP requirements and silicon timelines
Develop Python, Perl, and shell-based automation to improve simulation throughput, regression efficiency, and debug workflows

The Impact You Will Have

Deliver verified IP that ships in high-volume production SoCs powering AI, automotive, cloud, and mobile applications
Catch critical analog-digital interaction bugs before tapeout, directly preventing silicon respins and saving months of schedule and millions in cost
Build reusable AMS co-simulation frameworks that accelerate verification cycles for future SERDES generations and reduce time-to-market
Define verification methodologies that become the standard across Synopsys IPG teams, influencing how mixed-signal IP is verified company-wide
Enable first-pass silicon success for SERDES products deployed in top-tier customer designs, strengthening Synopsys reputation and customer trust
Mentor junior engineers and new graduates, raising the technical capability of the team and building institutional knowledge in AMS verification
Drive improvements in coverage metrics, simulation performance, and debug efficiency that make the entire verification flow more predictable and scalable

What You'll Need

Bachelor's degree with 5 years’ relevant experience or Master's degree with minimum of 3 years of relevant experience (Electrical Engineering, Computer Engineering, or related field.
Strong foundational understanding of analog and mixed-signal circuits including op-amps, bandgaps, PLLs, ADCs, TX/RX components, and high-speed interfaces
Proficiency with System Verilog and UVM for digital and mixed-signal testbench development
Experience with AMS simulation tools such as HSPICE, XA, CustomSim, or VCS AMS (for senior candidates, hands-on experience required; for new graduates, coursework or project exposure is sufficient)
Solid scripting skills in Python, Perl, or UNIX shell for automation and productivity improvements
For senior-level candidates, demonstrated experience in AMS co-simulation, SERDES verification, or behavioral modeling with a track record of owning verification flows and debugging complex analog-digital interactions
Experience with design reliability analysis including EM/IR checks is a plus

Who You Are

You can debug a failing co-simulation by isolating whether the issue is in the RTL, the analog netlist, the solver settings, or the testbench, and you know which log files and waveforms to check first
You do not wait for perfect documentation or complete specs, you ask the designer the right questions, build a test plan from what you know, and refine it as you learn more
You can explain a complex analog-digital interaction to a digital verification engineer or a coverage gap to an analog designer without losing either of them in jargon
You stay organized across multiple verification tasks, regression failures, and debug threads without dropping context or missing deadlines
You push back when a test plan is too shallow or a coverage metric does not actually prove what it claims to prove, and you do it constructively
You are comfortable mentoring others, whether that is walking a new graduate through their first UVM testbench or helping a colleague debug a tricky PLL convergence issue

The Team You'll Be Part Of

You will join the Synopsys IPG Co-Simulation team, a specialized group focused on verifying advanced Ethernet and PCIe SERDES IP used in top-tier SoCs across AI, automotive, cloud, and high-performance computing applications. The team collaborates closely with analog designers, digital verification engineers, modeling teams, and system architects across global Synopsys sites. This is a highly technical environment where AMS co-simulation expertise is valued, and where the verification work you do directly influence silicon success and customer deployments. The team supports both new graduates and experienced engineers, with mentorship structures and growth paths calibrated to experience level.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

AMS Design Verification Engineer

Job ID

19320

Country

Canada

City

Mississauga

State/Province

Mississauga

Date Posted

16-Oct-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

You will define and execute verification test plans for Ethernet and PCIe SERDES IP using UVM-based SystemVerilog testbenches and AMS co-simulation flows. Additionally, you will collaborate with cross-functional teams to debug complex analog-digital interactions and ensure design reliability through rigorous simulation and analysis.

Requirements

The role requires a Bachelor's degree with 5 years of experience or a Master's degree with 3 years of experience in Electrical or Computer Engineering. Candidates must possess strong foundational knowledge of analog and mixed-signal circuits, proficiency in SystemVerilog/UVM, and experience with industry-standard AMS simulation tools.

Skills

SystemVerilog
UVM
AMS co-simulation
HSPICE
XA
CustomSim
VCS
Python
Perl
Shell scripting
SERDES verification
Analog circuit design
Mixed-signal verification
Electromigration analysis
IR drop analysis
Testbench development

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

AMS Design Verification
Synopsys
SERDES
Ethernet
PCIe
SystemVerilog
UVM
HSPICE
XA
CustomSim
VCS
Python
Perl
Mixed-signal
Analog circuits
PLL
ADC
AFE
Electromigration
IR drop
RTL
Testbench
Simulation
Debugging
SoC
IPG
Automation
Regression
Verification methodology
Silicon success

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