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Nurse A - Registered Nurse General Duty Nurse
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…relating to the qualifications of the position. By submitting your application, you consent to your application history and talent profile being shared with Human Resources and the…
Added 1 hour ago
H
Nurse A - Registered Nurse General Duty Nurse
HealthCareersInSask.ca
Saskatoon, SK
- Full-time
…relating to the qualifications of the position. By submitting your application, you consent to your application history and talent profile being shared with Human Resources and the…
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Physician Assistant/Clinical Assistant- Psychiatry- 20091954; 20091955; 20091956; 20091915; 20091917
Winnipeg Regional Health Authority (WRHA)
Winnipeg, MB
- Part-time
Any application/CV received after the deadline closing date will be marked late and not included in the competition.

Synopsys

ASIC Design Verification Internship (16 Month Coop - Summer 2027)

Ottawa, ON, Canada

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Job details

Posting language: English
Posted: Oct 28, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are

Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide - and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement:

Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive - both at work and beyond.

What You'll Be Doing:

• Testbench Development: Work within a UVM (Universal Verification Methodology) testbench to verify SerDes ASIC RTL designs, gaining practical exposure to industry-standard verification frameworks.

• Protocol & Architecture Mastery: Develop in-depth knowledge of the PCIe protocol and the internal architecture of SerDes ASIC chips, understanding how cutting-edge hardware designs come to life.

• Advanced DV Methodology: Learn and apply comprehensive Design Verification (DV) concepts, including the Register Abstraction Layer (RAL), UVM phases, UVM objects, drivers, monitors, and scoreboards.

• Debugging & Analysis: Perform wave analysis and debug complex designs using industry-standard Synopsys tools such as Verdi, building critical problem-solving skills.

• Collaborative Learning: Work closely with senior engineers, participating in design reviews and team discussions to accelerate your professional growth and technical expertise.

What You'll Need:

• Education: Currently in 3rd or 4th-year standing, pursuing a bachelor's degree in Computer Engineering, Electrical Engineering, or a related field.

• Core Fundamentals: Strong foundational knowledge of Object-Oriented Programming (OOP) principles.

• Hardware Description: Familiarity with and ability to use SystemVerilog for hardware design and verification.

• Scripting: Proficiency in scripting languages, particularly Python, for automation and testing tasks.

• Soft Skills: A self-starter who is eager to learn, highly adaptable, and capable of picking up new and complex concepts quickly.

• Preferred Qualifications (Bonus): Familiarity or experience with MATLAB is a strong plus.

Key Program Facts:

• Program Length: 16-month co-op program

• Location: Kanata, Ottawa, Canada

• Working Model: Hybrid (2–3 days per week in-office)

• Full-Time/Part-Time: Full-Time

• Start Date: May 2027

Equal Opportunity Statement:

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

ASIC Design Verification Internship (16 Month Coop - Summer 2027)

Job ID

19523

Country

Canada

City

Kanata

State/Province

Kanata

Date Posted

28-Oct-2026

Job Category

Interns/Temp

Job Subcategory

Intern (Technical-Engineering)

Hire Type

Intern

Remote Eligible

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More about this job

Responsibilities

The intern will develop and maintain UVM testbenches to verify SerDes ASIC RTL designs while mastering PCIe protocols. They will also perform complex debugging and wave analysis using industry-standard tools like Verdi.

Requirements

Candidates must be in their 3rd or 4th year of a bachelor's degree in Computer or Electrical Engineering. Proficiency in SystemVerilog, Python, and Object-Oriented Programming principles is required.

Skills

UVM
SystemVerilog
Python
SerDes
PCIe
Verdi
Object-Oriented Programming
ASIC Design
Design Verification
Register Abstraction Layer
Wave analysis
Debugging
MATLAB

Benefits

Inclusive workplace
Collaborative environment
Professional growth opportunities
Mentorship

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Design Verification
UVM
SystemVerilog
Python
SerDes
PCIe
Verdi
RTL
Object-Oriented Programming
Register Abstraction Layer
Wave Analysis
MATLAB
Hardware Design
Automation
Semiconductor
Co-op

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