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Added 10 mins ago
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Responsible Investment Analyst, Temporary
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Vancouver, BC
- $65,000 to $75,000 CAD / year
- Full-time
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Added 26 mins ago
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- Full-time
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Synopsys

ASIC Digital Design, Sr Manager-18730

Mississauga, ON, Canada

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Job details

Experience: Minimum 2 years’ experience in people management and employee development.
Posting language: English
Posted: Sep 8, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SERDES PHY IP solutions.

Your leadership style is empowering, fostering growth and development within your team, and you’re committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and powers target while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you’re excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you.

What You’ll Be Doing:

Leading a diverse team of design engineering the development of next-generation SERDES PHY IP solutions.
Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.
Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
Mentoring and developing team members, fostering technical growth, and a culture of innovation.
Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

The Impact You Will Have:

Delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency.
Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
Enhancing product quality and reliability through rigorous design and verification processes/Flows.
Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

What You’ll Need:

Bachelor’s degree or higher in Electrical Engineering, with 15 +years of complex technical development experience.
Minimum 2 years’ experience in people management and employee development.
Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation.
Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA),CDC/RDC, DFT, and power optimization.
Excellent communication skills and the ability to work independently and collaboratively.
Understanding the PCIe and Ethernet standard is a plus.

Who You Are:

Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure.
Strong problem-solver with a strategic, analytical mindset.
Inspirational leader who motivates and develops technical talent.
Collaborative team players who excels in cross-functional environments.
Effective communicator who can translate complex technical concepts to diverse audiences.

The Team You’ll Be A Part Of:

You’ll join the Synopsys SERDES PHY IP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

ASIC Digital Design, Sr Manager-18730

Job ID

18730

Country

Canada

City

Mississauga

State/Province

Mississauga

Date Posted

08-Sep-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

Lead a diverse team in the development of next-generation SERDES PHY IP solutions from specification through productization. Collaborate with cross-functional teams including architecture, verification, and physical implementation to ensure optimal performance, timing, and power goals.

Requirements

Requires a Bachelor's degree or higher in Electrical Engineering with at least 15 years of complex technical development experience. Candidates must have a minimum of 2 years in people management and proficiency in front-end design flows and Verilog/System Verilog.

Skills

ASIC design
Verilog
System Verilog
Synthesis
Static timing analysis
Power optimization
SERDES PHY IP
Linting
CDC
RDC
DFT
PCIe
Ethernet
Leadership
Project management
Communication

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Digital Design
Semiconductor
Verilog
System Verilog
SERDES
PHY IP
Synthesis
Static Timing Analysis
Linting
CDC
RDC
DFT
Power Optimization
PCIe
Ethernet
SoC
Mixed-signal
Engineering Management
Productization
Silicon IP
Front-end flows
Technical Leadership
Hardware Design

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