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PV
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Synopsys

ASIC Digital Design, Sr Staff Engineer-19314

Markham, ON, Canada

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Job details

Experience: BS/MS in Electronics / Electrical Engineering or related fields with 8+ years of industry experience with digital verification methodology such as VMM/UVM
Posting language: English
Posted: Oct 16, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

The hiring manager is open to both Markham and Mississauga locations

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

A motivated and innovative ASIC digital verification engineer with relevant experiences. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from creating test plans to performing functional and performance tests on the test-chips/products.

What You'll Be Doing

Creating and updating test plans and test cases
Writing modular constrained-random/coverage driven Verilog, SystemVerilog
and UVM/VMM testbenches
Writing SystemVerilog assertions
Monitoring simulation regressions and debugging RTL and Gate level simulation failures
Writing functional coverage and performing functional/code/assertion coverage analysis
Tracking/Reporting issues in Jira and documenting in Confluence

What You'll Need

BS/MS in Electronics / Electrical Engineering or related fields with 8+ years of industry experience with digital verification methodology such as VMM/UVM
Solid experience in writing testcases in Verilog and System Verilog
Solid experience in debugging complex testbench and design related issues

Knowledge of high-speed digital & mixed-signal design
Solid understanding of digital circuit design
Basic understanding of C/C++ and RISC processors
Familiarity with scripting languages (Python or Perl)
Self learner/independent, good organization and communication skills

Skills desired:
* System Verilog Assertions / formal verification
* Good organization and communication skills

The Impact You Will Have

Catch critical bugs before tapeout that would otherwise cost months of schedule and significant silicon respins
Enable faster time-to-market for high-speed SerDes IP used in data center, automotive, and consumer products worldwide
Build reusable verification infrastructure that accelerates future product development and reduces verification cycle time
Improve coverage closure rates and regression stability, giving the team confidence to tape out on schedule
Mentor and influence verification methodology across the IP team, raising the bar for testbench quality and debug efficiency
Contribute to the success of mixed-signal products that power connectivity in millions of devices
Help shape verification strategy and tooling decisions that affect how the entire team works

Who You Are

You can look at a failing waveform with 50 signals toggling and zero in on the two that matter within minutes, not hours
You write testbenches that someone else can pick up six months later and actually understand what you were testing and why
You push back when a test plan is missing coverage for a critical corner case, and you do it in a way that makes the design team want to work with you
You are comfortable working across disciplines, talking to analog designers about settling time and digital architects about protocol compliance without losing the thread
You stay organized when managing multiple test plans, regression failures, and coverage gaps at once, and you know which fire to put out first
You learn new protocols, tools, and verification techniques without needing a formal training plan, you read the spec, try it, and figure it out

The Team You'll Be Part Of

You will work as part of a highly experienced mixed-signal design and verification team responsible for delivering SerDes IP for Backplane Ethernet, PCIe, SATA, and USB. The team includes both digital and analog engineers, and you will collaborate closely with both to verify designs from test plan creation through functional and performance validation on test chips and production silicon. This is a team that takes verification seriously and ships products that work.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

ASIC Digital Design, Sr Staff Engineer-19314

Job ID

19314

Country

Canada

City

Markham

State/Province

Markham

Date Posted

16-Oct-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

You will be responsible for verifying high-end mixed-signal products including Backplane Ethernet, PCIe, SATA, and USB SERDES. This involves creating test plans, writing modular testbenches, and debugging complex RTL and gate-level simulation failures.

Requirements

Candidates must have a BS/MS in Electrical Engineering or a related field with at least 8 years of industry experience in digital verification. Proficiency in SystemVerilog, UVM/VMM methodologies, and experience with high-speed digital design are required.

Skills

ASIC
Digital verification
SystemVerilog
Verilog
UVM
VMM
Constrained-random verification
Coverage driven verification
RTL debugging
Gate level simulation
Python
Perl
C/C++
Mixed-signal design
High-speed SerDes
Formal verification

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Digital Verification
SystemVerilog
Verilog
UVM
VMM
SerDes
PCIe
SATA
USB
Backplane Ethernet
RTL
Gate Level Simulation
Python
Perl
C++
RISC
Mixed-signal
Jira
Confluence
Formal Verification
Assertions
Functional Coverage
Code Coverage
Tapeout
Data Center
Automotive
Consumer Products
Silicon
IP

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