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Synopsys

ASIC Digital Verification, Sr. Manager

Mississauga, ON, Canada

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Job details

Experience: BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.
Posting language: English
Posted: Oct 5, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

You Are:

You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/SystemVerilog and are experienced in developing and managing testbenches in UVM environments. You are a natural leader with a proven track record of guiding and motivating teams to achieve their goals. Your expertise in high-speed interface protocols like PCIe/Ethernet and familiarity with IP design and verification tools positions you as an invaluable asset to any team. Your problem-solving skills, coupled with your ability to communicate effectively, enable you to navigate complex technical challenges and deliver high-quality solutions. You thrive in dynamic, multi-site environments and are driven by a passion for continuous learning and growth.

What You’ll Be Doing:

Specify, design, architect, and implement Digital Verification environments for our next-generation SERDES PHY IP solutions.
Lead a team, guiding them towards the closure of day-to-day verification activities.
Work closely with RTL designers, Architects, and Verification Engineers as part of a global team.
Understand design specifications and develop test plans and testbenches at both unit and system levels.
Ensure product release milestones are met through effective regression debug triaging and verification activities.
Contribute to the development and implementation of our next-generation SERDES PHY IP solutions, fostering a culture of continuous improvement and innovation.

The Impact You Will Have:

Drive the successful design and verification of high-performance memory controller IPs, contributing to the advancement of cutting-edge technology.
Ensure the timely and high-quality release of IP products that meet stringent industry standards.
Enhance the efficiency and effectiveness of design and verification processes through leadership and technical expertise.
Foster a collaborative and innovative team environment, enabling the professional growth and development of team members.
Support the strategic goals of Synopsys by contributing to the development of industry-leading IP solutions.
Strengthen Synopsys' reputation as a leader in the semiconductor industry through the delivery of high-quality, reliable products.

What You’ll Need:

BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.
Experience in leading a team of engineers and guiding them towards achieving project milestones.
Hands-on experience in verification of complex designs at the IP or SoC level.
Strong knowledge of Verilog/SystemVerilog and experience in developing testbenches in UVM environments.
Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills.
Understanding the PCIe and Ethernet standards is a plus.

Who You Are:

A strong team leader and motivator with a go-getter attitude.
A technical contributor with expertise in SystemVerilog testbench development.
Capable of creating deliverables that meet high standards without requiring close supervision.
Skilled in understanding design and verification milestones and aligning team tasks accordingly.
Experienced in improving coverage metrics and defining additional test cases.
Familiar with HDLs such as Verilog and scripting languages like shell/Perl/Python.
A good team player with strong interpersonal and communication skills.
Highly motivated and self-propelled, thriving in a project and team-oriented environment.

The Team You’ll Be A Part Of:

You’ll join the Synopsys SERDES PHY IP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

ASIC Digital Verification, Sr. Manager

Job ID

19159

Country

Canada

City

Mississauga

State/Province

Mississauga

Date Posted

05-Oct-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

Lead a team in the design, architecture, and implementation of digital verification environments for next-generation SERDES PHY IP solutions. Collaborate with RTL designers and architects to ensure product release milestones are met through effective test planning and regression debugging.

Requirements

Requires a BS/MS in EE/EC/VLSI with over 15 years of relevant experience in IP core or SoC verification. Candidates must possess strong expertise in SystemVerilog, UVM, and team leadership within complex semiconductor design environments.

Skills

ASIC
Digital Verification
SystemVerilog
Verilog
UVM
SERDES
PHY IP
PCIe
Ethernet
Perl
Python
Team Leadership
Testbench Development
RTL Design
Regression Debugging
VLSI

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Digital Verification
SystemVerilog
Verilog
UVM
SERDES
PHY IP
PCIe
Ethernet
Perl
Python
VLSI
Semiconductor
IP Cores
SoC
Regression Debugging
Testbench
RTL
Team Leadership
Engineering
Hardware Design
Automation
Memory Controller
Silicon IP
High-speed Interface

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