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Added 1 hour ago
Gestionnaire de performance, Québec city
AutoTrader.ca
Quebec, QC
…opérations, leur marketing et leurs ventes. Dealertrack Canada est le principal portail de financement automobile au pays, traitant plus de 6,5 millions de demandes de crédit chaque année.…
Added 2 hours ago
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Gestionnaire de performance, Québec city
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Quebec, QC
- Full-time
…opérations, leur marketing et leurs ventes. Dealertrack Canada est le principal portail de financement automobile au pays, traitant plus de 6,5 millions de demandes de crédit chaque année.…
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Principal Data Architect, FSI
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- Full-time
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Principal Consultant – AWS Data Platforms & Agentic AI
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Commercial Principal, Corporate Insights – Technology & Software (North America)
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Principal Data Scientist
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Added 3 days ago
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Principal Product Manager (AI)
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Senior Solutions Architect (Pre-Sales)
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Principal Consultant, Secure Microsoft 365 Collaboration and AI
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Principal Architect
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- $200,000 CAD / year
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Added 4 days ago
Principal Analog Design Engineer-19318
Synopsys
Markham, ON
Influence circuit architecture decisions that shape Synopsys Solution IP product roadmaps
Added 4 days ago
Chef d’équipe, Gestion des commandes – Opérations de vente au détail // Team Lead, Retail Operations Order Management
SharkNinja
Montreal, QC
Agir comme principal point de contact entre l’équipe et les partenaires interfonctionnels pour les enjeux quotidiens de gestion des commandes, en assurant un suivi et une résolution rapides.

Synopsys

Principal Analog Design Engineer-19318

Markham, ON, Canada

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Job details

Experience: PhD with 6+ years or Master's with 8+ years of analog and mixed-signal IC design experience
Posting language: English
Posted: Oct 16, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing circuits that operate at the edge of what physics allows, and you know that the difference between a PHY that meets spec and one that ships is usually traced back to a layout decision, a bias choice, or a parasitic you anticipated six months earlier. You are the kind of engineer who reads JEDEC standards not to check a box but to find the constraints that matter, then architects around them.

You are comfortable moving between SPICE simulations, layout reviews, and whiteboard sessions with digital designers without losing sight of what you are building. When someone says "we need better power efficiency," you do not nod and move on. You ask which corner, which mode, and what we are willing to trade. You have designed enough VCOs, PLLs, samplers, or drivers to know what breaks under process variation, and you catch it before tape-out.

**Other locations can be considered for this opportunity but must reside in Canada.

What You'll Be Doing

* Review JEDEC standards to define analog and mixed-signal sub-block specs for DDR/LPDDR, HBM, UCIe, and mobile storage PHY IP
* Design transistor-level circuits including equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgap references, ADCs, and DACs
* Develop verification strategies using SPICE simulators and Verilog-A models to ensure coverage across PVT corners
* Collaborate with layout engineers to minimize parasitics, manage device stress, and implement ESD protection
* Present simulation data and design tradeoffs to internal teams and customers
* Document circuit designs, test plans, and reliability considerations for tape out
* Consult on electrical characterization and silicon bring-up to validate your circuits in the final product

The Impact You Will Have

* Enable next-generation memory and interconnect solutions that define performance benchmarks for DDR, LPDDR, and HBM standards
* Deliver power-efficient, high-speed analog circuits in advanced FinFET nodes
* Reduce tape out risk through rigorous simulation and early identification of layout issues
* Influence circuit architecture decisions that shape Synopsys Solution IP product roadmaps
* Contribute to IP products that accelerate customer time to market for AI, mobile, automotive, and data center applications

What You'll Need

* PhD with 6+ years or Master's with 8+ years of analog and mixed-signal IC design experience
* Deep expertise in transistor-level CMOS design with strong fundamentals in device physics and matching
* Proven experience designing circuits in FinFET process technologies
* Detailed design experience with high-speed sub-circuits: equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgaps, ADCs, or DACs
* Working knowledge of ESD protection techniques and layout strategies
* Proficiency with schematic entry, SPICE simulation (Spectre, HSPICE), and design verification tools
* Strong understanding of design-for-reliability including electromigration, IR drop, aging, and layout-dependent effects

Who You Are

* You can look at a circuit topology and immediately identify the second-order effects that will matter at corner cases
* You communicate tradeoffs clearly, whether explaining a bias decision to a layout engineer or presenting jitter analysis to customers
* You push back when a specification does not make physical sense, and you do it in a way that moves the team forward
* You are comfortable scripting in Python, Perl, TCL, MATLAB, or C to automate simulation flows and build custom analysis tools
* You document your work clearly enough that someone else can pick up your design six months later and understand why you made each decision

The Team You'll Be Part Of

You will join the Solution IP R&D team, a collaborative group of analog and digital designers developing high-speed PHY IP for DDR/LPDDR, HBM, UCIe, and mobile storage applications. The team works in a best-in-class design environment with a full suite of IC design tools, custom in-house automation, and support from an experienced CAD and software team.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

Principal Analog Design Engineer-19318

Job ID

19318

Country

Canada

City

Markham

State/Province

Markham

Date Posted

16-Oct-2026

Job Category

Engineering

Job Subcategory

Analog Design

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

Define analog and mixed-signal specifications based on JEDEC standards, and design and verify transistor-level circuits for memory and interconnect PHY IP across process, voltage, and temperature corners. Collaborate with layout and cross-functional teams to address parasitics, reliability, and ESD, document designs for tape-out, and support characterization and silicon bring-up.

Requirements

Requires a PhD with at least 6 years or a master's degree with at least 8 years of analog and mixed-signal IC design experience, including transistor-level CMOS design and FinFET technologies. Candidates should have experience with high-speed analog subcircuits, SPICE and design verification tools, ESD and layout strategies, reliability considerations, and scripting for automation.

Skills

Analog And Mixed-Signal IC Design
Transistor-Level CMOS Design
FinFET Process Technologies
High-Speed PHY Circuit Design
Equalizers
Samplers
Drivers And Serializers
VCOs, PLLs, And DLLs
Bandgap References
ADCs And DACs
SPICE Simulation
Verilog-A Modeling
ESD Protection
Design For Reliability
Python, Perl, TCL, MATLAB, Or C Scripting

Benefits

Health Benefits
Wellness Benefits
Financial Benefits

Visa sponsorship

Not detected in the job text

Keywords

JEDEC Standards
DDR
LPDDR
HBM
UCIe
Mobile Storage PHY
Analog And Mixed-Signal Design
CMOS
FinFET
SPICE
Spectre
HSPICE
Verilog-A
PVT Corners
ESD Protection
Electromigration
IR Drop
Device Aging
Layout-Dependent Effects
Schematic Entry
Circuit Verification
Electrical Characterization
Silicon Bring-Up
Tape-Out
Python
Perl
TCL
MATLAB
C
Solution IP

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