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Synopsys

Principal Digital Verification Engineer

Ottawa, ON, Canada

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Job details

Experience: BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years
Posting language: English
Posted: Sep 8, 2026

Original job description

General Information

Job Title

Principal Digital Verification Engineer

Job ID

18733

Country

Canada

City

Nepean

State/Province

Nepean

Date Posted

08-Sep-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building verification environments for complex digital designs where mistakes show up as silicon respins or customer escalations. The difference between a PHY that passes regression and one that works in production is something you understand deeply, and it shapes how you write testplans, model coverage, and design infrastructure.

The testbenches you build are meant to last. You have inherited enough unmaintainable code to know what matters when a project needs to scale across multiple product generations. Working across distributed teams is something you have done enough times to know when to align closely with architects on protocol details and when to just push forward on debug with RTL and firmware engineers in other time zones.

Technical reviews matter to you because that is where you can catch verification risks before they become schedule problems. At Synopsys, you will work on memory interface IP with a team that takes verification seriously as its own discipline, not just a gate before tapeout.

What You'll Be Doing

Develop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs
Build and maintain testbench infrastructure in SystemVerilog and UVM that supports complex verification scenarios across multiple product generations
Create test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements
Debug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools
Participate in technical reviews with architecture and implementation teams to influence design decisions from a verification perspective
Research and evaluate emerging technologies in virtual prototyping and emulation to improve team efficiency, throughput, and quality
Mentor junior engineers on testbench design, debugging techniques, and verification methodology while collaborating with other principal-level engineers on verification strategy

The Impact You Will Have

Your testplans and coverage models will define the quality bar for memory interface IP that powers next-generation products across the industry
The testbench infrastructure you build will accelerate verification cycles and enable the team to scale as new product lines come online
Your debugging expertise will catch critical issues before they reach customers, protecting both product schedules and Synopsys reputation
Technical reviews you contribute to will shape architecture decisions early, preventing costly verification bottlenecks downstream
New verification technologies you evaluate and adopt will directly improve team productivity and reduce verification time
Engineers you mentor will carry forward the verification rigor and problem-solving approach that makes complex IP actually work
Your work with customers (on simulation debug or post-silicon bring-up debug) will strengthen their confidence in our IP and inform future product roadmaps

What You'll Need

BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years
Deep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments
Strong command of simulation tools, waveform debuggers, and the ability to trace issues across multiple abstraction layers
Solid understanding of C and experience with software/hardware co-simulation
Experience with assertion-based verification, coverage analysis, and protocol-oriented performance debug
Comfort working in Linux environments with scripting for regression systems, build automation, and source control workflows
Experience with virtual prototyping or emulation platforms is a strong plus, as is knowledge of LPDDR5/5X and LPDDR6 or other memory interface standards

Who You Are

You can read a functional spec and immediately start sketching out the test scenarios that will stress the design in ways the architects did not anticipate
You work effectively across distributed teams without needing constant check-ins, you know when to sync up and when to just make progress
You bring a point of view to design reviews and you are not afraid to flag a verification risk even if it means pushing back on a schedule
You balance thoroughness with pragmatism, you know when a testbench needs another week of work and when it is good enough to start finding real bugs
You explain complex verification trade-offs clearly enough that an architect or project manager understands the risk without needing a deep dive into UVM internals

The Team You'll Be Part Of

You will join the IP Group in Ottawa, a team focused on developing interface IP solutions for memory interfaces. The team is international, with members collaborating across multiple time zones to deliver IP that ships into high-volume products. You will work alongside other principal-level verification engineers, contributing to verification strategy while also building and executing on testplans. The group values technical depth, rigorous methodology, and the kind of verification work that actually prevents customer issues rather than just checking compliance boxes.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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More about this job

Responsibilities

Develop comprehensive testplans and functional coverage models for memory PHY firmware while building and maintaining robust UVM-based testbench infrastructure. Debug complex issues across firmware, RTL, and testbench layers while mentoring junior engineers and influencing design decisions through technical reviews.

Requirements

Requires a BSc, MSc, or PhD in Electrical or Computer Engineering with 8 to 12+ years of relevant verification experience. Candidates must possess deep proficiency in SystemVerilog, UVM, and simulation tools, along with experience in hardware/software co-simulation and Linux-based workflows.

Skills

SystemVerilog
UVM
Digital verification
Memory interface IP
RTL
Firmware
Simulation
Waveform analysis
Functional coverage
Testbench infrastructure
Linux
Scripting
Assertion-based verification
C
Hardware/software co-simulation
Debugging

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

SystemVerilog
UVM
ASIC
Digital Design
Memory Interface IP
RTL
Firmware
Verification
Testbench
Simulation
Waveform Analysis
Functional Coverage
Linux
Scripting
Assertion-based Verification
C
Hardware/Software Co-simulation
Virtual Prototyping
Emulation
LPDDR5
LPDDR5X
LPDDR6
Regression
Build Automation
Source Control
Debugging
Architecture
Protocol
Silicon
IP

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