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Added 25 days ago
Principal Firmware Engineer
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Experience with Python and Verilog is a strong plus, particularly for test automation and RTL co-development
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Synopsys

Principal Firmware Engineer

Ottawa, ON, Canada

Apply on synopsys.avature.net About employer

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Job details

Posting language: English
Posted: Sep 8, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

Firmware at the boundary between hardware and software is where you have built your career. A single miscalculation can mean the difference between a memory interface that trains cleanly and one that fails in the field, and that reality has shaped how you work. Performance is not just about writing tight code. It is about understanding what the silicon is actually doing when your code runs at boot time.

Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find microcode level bottlenecks is the kind of work that keeps you engaged. The hardware is real, the constraints are real, and the problems do not solve themselves with abstractions.

Mentoring others matters to you, but so does staying curious about how new modeling techniques might change what is possible.

At Synopsys, the memory interface PHYs you work on will power the next generation of DDR, LPDDR, and HBM solutions.

What You'll Be Doing

Develop and optimize firmware for DDR, LPDDR, and HBM memory interface PHY training sequences
Profile compiled firmware at the instruction level to identify runtime bottlenecks and implement optimizations that improve training performance
Analyze RTL waveforms and testchip data in the hardware lab to understand eye margin sensitivity and refine training algorithms
Collaborate with firmware architecture to study JEDEC protocol specifications and propose algorithmic improvements to training workflows
Debug complex hardware-software interaction issues across firmware, RTL, and physical silicon using lab equipment and simulation tools
Explore and prototype how emerging modeling techniques could be applied to memory training workflows
Mentor engineers on the team, sharing your knowledge of embedded firmware development, hardware debugging, and memory interface behavior

The Impact You Will Have

Reduce training runtime for next-generation memory PHYs, directly improving customer time-to-market and system boot performance
Improve training robustness and eye margin across process, voltage, and temperature corners, resulting in higher yield and reliability for customer designs
Influence the architecture of future PHY training algorithms by bringing fresh perspectives grounded in real hardware behavior
Accelerate team capability by mentoring engineers on low-level firmware optimization, RTL debugging, and protocol-level problem solving
Enable Synopsys to deliver competitive, high-performance memory IP solutions that meet the demands of AI, HPC, and data center applications
Shape the direction of firmware development practices and tooling within the IP Group through your technical leadership
Contribute to the successful deployment of memory PHY IP used by leading semiconductor companies worldwide

What You'll Need

Bachelor's degree in Engineering, Computer Science, or related field with 12+ years of software development experience, Master's with 10+ years, or PhD with 8+ years, all in commercial or production environments
Deep proficiency in C for embedded firmware development, including experience optimizing for resource-constrained processors
Hands-on experience with RTL waveform analysis and debugging using tools like Verdi, DVE, or similar
Demonstrated ability to work at the hardware-software boundary, understanding how firmware interacts with digital logic and physical interfaces
Experience profiling and optimizing compiled code for performance-critical applications
Strong debugging skills across firmware, RTL simulation, and hardware lab environments
Experience with Python and Verilog is a strong plus, particularly for test automation and RTL co-development

Who You Are

When a training algorithm in a JEDEC spec catches your eye, your mind immediately goes to edge cases, corner conditions, and where the runtime cost will hide
Working in a hardware lab with testchips, probing signals, and correlating scope traces with firmware behaviour is second nature to you
Debugging means profiling, tracing, and looking at waveforms until the root cause reveals itself, not guessing your way through
Bringing ideas to the table is important to you, and so is being open to pushback or defending a position when it matters
Explaining a firmware optimization to a hardware engineer or a training strategy to a customer-facing team is something you can do without losing either audience
Mentoring by showing is your style, walking someone through a debug session or profiling workflow until they can own it themselves

The Team You'll Be Part Of

You will be part of the Synopsys IP Group firmware development team based in Ottawa, focused on developing interface IP solutions for DDR, LPDDR, and HBM memory interfaces. The team works on the challenging problem of PHY-to-memory interface training for next-generation protocols and bus speeds, balancing runtime performance with quality of results. This is a team that values fresh perspectives and is committed to mentoring and integrating new members. You will have access to an advanced hardware lab with a library of testchips for real-world validation and optimization work.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

Principal Firmware Engineer

Job ID

18736

Country

Canada

City

Nepean

State/Province

Nepean

Date Posted

08-Sep-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

Apply on synopsys.avature.net About employer

More about this job

Responsibilities

Develop and optimize firmware and training algorithms for DDR, LPDDR, and HBM memory PHYs, using instruction-level profiling, RTL waveforms, simulation, and testchip data to improve performance and robustness. Debug hardware-software issues, explore modeling techniques, collaborate on protocol and architecture improvements, and mentor engineers.

Requirements

Requires a bachelor's degree and 12+ years, a master's degree and 10+ years, or a PhD and 8+ years of commercial or production software development experience. Candidates need deep embedded C expertise, compiled-code optimization and profiling experience, RTL waveform debugging skills, and hands-on experience across firmware, simulation, and hardware lab environments; Python and Verilog are strong pluses.

Skills

Embedded C Firmware Development
Firmware Optimization
DDR, LPDDR, and HBM Memory Interfaces
PHY Training Algorithms
RTL Waveform Analysis
Hardware-Software Debugging
Compiled Code Profiling
JEDEC Protocol Specifications
Hardware Lab Testing
Python
Verilog
Test Automation
Mentoring
Memory Interface Behavior

Benefits

Health Benefits
Wellness Benefits
Financial Benefits

Visa sponsorship

Not detected in the job text

Keywords

Embedded Firmware
C
Python
Verilog
DDR
LPDDR
HBM
Memory PHY
PHY Training
JEDEC
RTL
RTL Waveforms
Verdi
DVE
Instruction-Level Profiling
Compiled Code Optimization
Hardware-Software Integration
Hardware Debugging
Firmware Architecture
Testchips
Hardware Lab
Simulation Tools
Test Automation
Eye Margin
Process, Voltage, and Temperature Corners
Memory Interface IP
ASIC Digital Design
Firmware Development
Algorithm Optimization
Mentoring

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Jobs in Canada