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Synopsys

Principal Physical Design Methodology Engineer

Markham, ON, Canada

Experience: Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10+ years of hands-on ASIC digital implementation experience
Posting language: English
Posted: Aug 15, 2026

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Original job description

General Information

Job Title

Principal Physical Design Methodology Engineer

Job ID

18396

Country

Canada

City

Markham

State/Province

Markham

Date Posted

15-Aug-2026

Job Category

Engineering

Job Subcategory

R&D Engineering

Hire Type

Employee

Remote Eligible

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building the kind of high-speed digital IP that actually ships in products people use, and you know the difference between a flow that looks good in a deck and one that survives contact with a 3nm tapeout schedule. Somewhere along the way, you stopped being the engineer who executes the methodology and became the one who writes it, debugs it when it breaks at 2am, and teaches three teams across two continents how to use it without losing your patience.

You think in tradeoffs. PPA is not a buzzword to you, it is the conversation you have every day with designers who want faster clocks, lower power, and smaller area, and you are the one who figures out which two they can actually have. You have opened Fusion Compiler or ICC2 enough times that you know where the tools break down, and you have written enough Tcl and Python to automate your way around those edges.

You do not wait for perfect requirements. You sit with a design team, ask what they are actually trying to build, and walk out with a methodology plan that works. At Synopsys, you will define the RTL-to-GDSII flows that power the next generation of SerDes and memory controllers, and the engineers who use your work will know your name.

What You'll Be Doing

Lead the digital methodology engineering effort for Interface IP, defining and maintaining the complete RTL-to-GDSII implementation flow using Fusion Compiler, PrimeTime, PrimePower, and related Synopsys toolchains
Build, test, and deploy synthesis and place-and-route methodologies for high-speed IP cores and subsystems targeting advanced nodes (5nm, 3nm, and beyond)
Evaluate and optimize design-for-test insertion, timing closure, power optimization, and EM/IR analysis workflows across multiple IP development teams
Develop automation scripts, reference flows, and documentation that design teams can actually use without calling you every time something breaks
Act as the technical bridge between EDA tool development teams and IP design teams, translating tool capabilities into usable methodology and feeding real-world design challenges back to tool teams
Mentor engineers across global teams on digital implementation best practices, timing closure strategies, and physical design tradeoffs
Drive continuous improvement of design processes by identifying bottlenecks, proposing solutions, and measuring impact on PPA and schedule

The Impact You Will Have

Your methodologies will directly determine the PPA outcomes for Synopsys Interface IP products used by semiconductor companies worldwide
Design teams will close timing weeks faster because the flows you built handle corner case scenarios and multi-mode optimization without manual intervention
You will enable IP teams to adopt new process nodes and EDA tool versions with confidence, reducing risk and accelerating time to tapeout
Engineers you train will carry forward the practices you establish, multiplying your impact across dozens of projects and hundreds of tapeouts
Your feedback loop with EDA tool teams will shape the next generation of Synopsys synthesis and place-and-route capabilities
The automation and reference flows you create will become the foundation for how Synopsys develops high-speed digital IP for years to come
You will help Synopsys maintain its position as the provider of best-in-class IP by ensuring every design starts with a world-class implementation methodology

What You'll Need

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10+ years of hands-on ASIC digital implementation experience
Deep expertise with Fusion Compiler or equivalent industry synthesis and place-and-route tools (ICC2, Innovus), including advanced features like multi-mode multi-corner optimization, clock tree synthesis, and physical synthesis
Proven track record developing or supporting high-speed digital IP cores or SoCs, ideally in SerDes, memory controllers, or similar high-performance designs
Strong understanding of the full ASIC physical design flow including IP deliverables, memory compilers, standard cell libraries, and process design kits
Solid scripting skills in Tcl and Python for flow automation, analysis, and reporting
Experience with Synopsys timing and power analysis tools like PrimeTime, PrimePower, RLTA, or CoreTools is a strong plus
Familiarity with high-speed interface protocols such as PCIe, DDR, USB, Ethernet, HDMI, MIPI, or DisplayPort is a strong plus

Who You Are

You can sit in a design review, listen to a timing closure problem, and sketch out three possible solutions on a whiteboard without needing to run back to your desk first
You write documentation that engineers actually read because it is clear, practical, and includes the gotchas you learned the hard way
You are comfortable saying "that will not work" when a proposed approach has a fatal flaw, and you can explain why in terms the team understands and respects
You debug methodically, not randomly. When a flow breaks, you isolate the variable, reproduce the issue, and fix it in a way that prevents it from happening again
You can explain a complex PPA tradeoff to a design lead in two sentences without losing the technical nuance, and you can explain the same tradeoff to a tool developer in the level of detail they need to act on it
You mentor without taking over. You show engineers how to solve the problem, not just what the answer is, because you know that builds stronger teams

The Team You'll Be Part Of

You will join the Interface IP Digital Design Methodology team, a global group responsible for defining and maintaining the ASIC design standards and flows that support Synopsys IP development teams. This team works directly with next-generation SerDes and memory interface controllers, PHYs, and subsystems, and collaborates closely with both IP design teams and EDA tool development teams across North America, Europe, and Asia. You will be part of a technical community that values deep expertise, practical problem solving, and the kind of collaboration that happens when engineers respect each other's work.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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More about this job

Responsibilities

Lead the digital methodology engineering effort for Interface IP by defining and maintaining the complete RTL-to-GDSII implementation flow. Develop automation scripts and mentor global teams on best practices for timing closure and physical design tradeoffs.

Requirements

Requires a Bachelor's or Master's degree in Electrical or Computer Engineering with over 10 years of hands-on ASIC digital implementation experience. Candidates must possess deep expertise in synthesis and place-and-route tools, along with strong scripting skills in Tcl and Python.

Skills

Physical design
RTL-to-GDSII
Fusion Compiler
ICC2
PrimeTime
PrimePower
Tcl
Python
ASIC
Timing closure
PPA optimization
SerDes
Memory controllers
Synthesis
Place-and-route
Design-for-test

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

Physical Design
RTL-to-GDSII
Fusion Compiler
ICC2
PrimeTime
PrimePower
ASIC
Tcl
Python
SerDes
Memory Controllers
Synthesis
Place-and-Route
PPA
Timing Closure
Design-for-Test
EM/IR Analysis
Interface IP
3nm
5nm
Clock Tree Synthesis
Physical Synthesis
PCIe
DDR
USB
Ethernet
HDMI
MIPI
DisplayPort
Methodology

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