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Synopsys

Senior Verification Manager, SERDES PHY

Mississauga, ON, Canada

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Job details

Experience: 10+ years of hands-on ASIC mixed-signal verification experience with recent work in the last 3 to 5 years on debug, environment development, or sign-off
Posting language: English
Posted: May 25, 2026

Original job description

General Information

Job Title

Senior Verification Manager, SERDES PHY

Job ID

17631

Country

Canada

City

Mississauga

State/Province

Mississauga

Date Posted

25-May-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade-plus in mixed-signal verification and you know that SERDES PHY is where theory meets silicon reality, where a clean testplan does not guarantee clean bring-up, and where the difference between a release and a respin often lives in one corner case nobody caught at 100°C. You are technical first, manager second. You can walk into a regression triage meeting, pull up waveforms, spot the PLL lock issue or the CDR drift that three engineers missed, and coach them through root cause without taking over their keyboard.

Leading people matters to you, but not at the expense of staying credible. You review UVM environments, you read coverage reports, you understand what makes a mixed-signal co-sim model trustworthy versus theatrical. When a customer escalation lands on your desk, you do not delegate it, you get into the debug alongside your team because that is how you stay sharp and that is how they learn.

You have run teams before. You know how to hire, grow senior leads, set priorities when everything is on fire, and say no when a feature request will compromise sign-off quality. At Synopsys, you will lead verification for flagship SERDES PHY IP that powers high-performance SoCs, and you will do it with your hands still in the work.

What You'll Be Doing

Lead and grow a distributed team of verification engineers and senior technical leads working on SERDES PHY mixed-signal verification across UVM simulation, co-simulation, emulation, and lab validation
Debug priority regressions, customer escalations, and silicon correlation issues directly, working in SystemVerilog, UVM, co-sim environments, and firmware bring-up flows
Own verification sign-off quality and release readiness for SERDES PHY IP, including testplan review, coverage analysis, checker effectiveness, and release evidence documentation
Define and evolve UVM and mixed-signal co-simulation methodology, regression standards, reuse strategy, and automation frameworks using Shell, Perl, Python, and C++
Partner daily with analog design, digital design, firmware, and applications teams to resolve technical blockers, align on test strategy, and close coverage gaps
Represent verification in program reviews, customer technical engagements, and cross-functional release planning meetings
Drive automation and AI-assisted regression triage where it measurably improves throughput, debug time, or coverage closure

The Impact You Will Have

Ensure SERDES PHY IP releases meet sign-off quality for deployment in high-performance SoCs shipping to customers across automotive, data center, and AI markets
Reduce time to root cause on mixed-signal bugs by building a team that knows how to read waveforms, correlate models to silicon, and close issues without escalation loops
Establish verification methodology and reuse standards that scale across PCIe, Ethernet, and future high-speed serial IP families
Grow senior verification engineers into technical leads who can own testplans, drive coverage closure, and mentor others through complex debug
Improve regression efficiency and triage speed through targeted automation, better VIP integration, and smarter use of co-simulation and emulation platforms
Strengthen customer confidence in Synopsys SERDES IP by delivering clean releases, fast escalation response, and credible technical partnership during bring-up
Shape the technical direction of mixed-signal verification at Synopsys by contributing to tool selection, flow improvements, and cross-team best practices

What You'll Need

10+ years of hands-on ASIC mixed-signal verification experience with recent work in the last 3 to 5 years on debug, environment development, or sign-off
3+ years leading verification engineers or equivalent team lead scope, including hiring, performance management, and technical mentorship
Deep experience with PCIe and/or Ethernet SERDES, high-speed serial links, DSP blocks, and clock/data recovery circuits
Strong command of SystemVerilog, UVM, VIP integration, and coverage-driven verification methodology
Proven ability in mixed-signal verification flows including co-simulation, analog/digital modeling, and lab or silicon correlation
Scripting proficiency in Shell, Perl, Python, or C++ with the ability to review and contribute to automation infrastructure
Credible technical judgment under schedule pressure, you know when to push for more coverage and when to ship with documented risk. Experience with TX/RX PMA, common-mode PLLs, firmware bring-up, or rate and power state flows is a plus. Distributed team leadership with hands-on technical engagement is a strong differentiator.

Who You Are

You can step into a regression triage, pull up a waveform in Verdi or DVE, and guide an engineer to the root cause without doing the work for them
You know the difference between a testplan that looks complete and one that actually covers the corner cases that break in the lab, and you push back when sign-off evidence is thin
You are comfortable switching context between a hiring conversation, a firmware debug session, a customer call, and a coverage review, all in the same afternoon
You build teams that stay technical, you hire people who want to understand the PHY, not just run regressions, and you create space for them to grow into senior leads
You do not need perfect information to make a call, you work with what you have, align with design and firmware, and move forward without creating downstream chaos
You care about automation and tools, but only when they solve a real problem, you will write a Python script to fix a triage bottleneck and you will kill a dashboard nobody uses

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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More about this job

Responsibilities

Lead and grow a distributed team of verification engineers while maintaining hands-on involvement in debug, testplan review, and silicon correlation. Define verification methodologies and ensure sign-off quality for high-performance SERDES PHY IP across various simulation and validation platforms.

Requirements

Requires 10+ years of hands-on ASIC mixed-signal verification experience and 3+ years of team leadership experience. Candidates must possess deep expertise in high-speed serial links, SystemVerilog, UVM, and mixed-signal co-simulation flows.

Skills

Mixed-signal verification
SERDES PHY
SystemVerilog
UVM
Co-simulation
Emulation
Lab validation
PCIe
Ethernet
Shell
Perl
Python
C++
Firmware bring-up
Coverage-driven verification
Team leadership

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

ASIC
Digital Design
SERDES PHY
Mixed-signal
Verification
UVM
SystemVerilog
PCIe
Ethernet
Co-simulation
Emulation
Firmware
Shell
Perl
Python
C++
Verdi
DVE
Regression
Coverage analysis
Silicon correlation
Automation
IP
SoC
DSP
Clock and data recovery
PMA
PLL
Technical leadership
Sign-off

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