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Added 7 mins ago
WI
Lead Instrumentation & Control Engineer, Resources
WSP in Canada
Markham, ON
- Full-time
…Greater Toronto Area, Saskatoon SK, St John's NL as a Lead I&C Engineer, you will support as a senior subject matter expert in the instrumentation and controls engineering for both new…
Added 7 mins ago
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Senior Project Engineer
ABB
Calgary, AB
- Full-time
ABB is seeking a Senior Lead Project Engineer to join our team. In this role, you will provide technical leadership and oversee the successful execution of multidisciplinary electrical…
Added 7 mins ago
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Electrical Engineer
LAPORTE
AB · Edmonton, AB
- Full-time
Electrical Engineer – Calgary, Edmonton or Lethbridge
Added 7 mins ago
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Electrical Engineer
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- Full-time
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Added 7 mins ago
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Markham, ON
- $70 to $80 USD / hour
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Added 38 mins ago
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Added 38 mins ago
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Calgary, AB
Our rapidly growing Industrial Engineering team, which includes process, mechanical, electrical, controls, structural, architectural, geotechnical, and civil disciplines, is a multi-faceted…
Added 53 mins ago
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Mechanical Engineer, Data Centers
AECOM
Markham, ON
- $90,000 to $145,000 CAD / year
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- $125,000 to $175,000 CAD / year
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Added 53 mins ago
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Senior Mechanical Engineer, Data Centers
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Markham, ON
- $125,000 to $175,000 CAD / year
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Design Manager, Data Centers
AECOM
Markham, ON
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Warranty Engineer
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Vaughan, ON
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Principal ASIC Design Engineer
AMD
Markham, ON
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Synopsys

Sr Staff Package Design Engineer

Ottawa, ON, Canada

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Job details

Experience: 10+ years of hands-on experience in semiconductor package design, package substrate layout, electrical modeling, or closely related work
Posting language: English
Posted: Sep 22, 2026

Original job description

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

Having spent a decade or more working at the intersection of silicon, packaging, and board design, you know where good architectures succeed and where they fail. Evaluating package architectures, reviewing power delivery networks and bump maps, and turning SI/PI and EM analysis into sound engineering decisions are all part of your toolkit. When faced with ambiguity, you know how to focus on the issues that matter and keep complex programmes moving forward.

At Synopsys, you'll lead package design for advanced IP test chips at the forefront of performance. Working with tools such as Ansys HFSS and collaborating across engineering teams, you'll help shape the technologies that enable the next generation of semiconductor products. Just as importantly, you'll bring the confidence to challenge assumptions, ask the right questions, and drive decisions that move the design forward.

What You'll Be Doing

Lead four to six test-chip package designs per year from requirements definition through final delivery, coordinating across internal teams, customers, and external partners

Define package requirements early in the design cycle, including bump maps, ball maps, and layer stack-up decisions that optimize signal integrity and power integrity performance

Perform hands-on physical design and layout of advanced package substrates using industry-standard EDA tools

Extract electrical models from substrate designs using 3D EM simulation tools like Ansys HFSS, and analyze them against SI and PI requirements to validate performance

Guide customers through package architecture evaluations and tradeoff analysis to identify implementation options that work for Synopsys IP

Resolve complex package design and integration issues by developing technically sound solutions that balance electrical performance, manufacturability, and cost

Provide regular project updates to management covering progress, technical risks, dependencies, mitigation plans, and decisions that need escalation

The Impact You Will Have

Enable successful tape-outs of Synopsys IP test-chips by ensuring package designs meet electrical and physical performance requirements from day one

Reduce design iteration cycles and avoid costly respins by catching signal integrity and power integrity issues early through rigorous modeling and analysis

Expand the range of package solutions available to Synopsys customers by evaluating new architectures and proving out their viability for high-performance IP

Strengthen customer relationships by providing expert guidance on package design decisions that directly affect their product success

Improve design quality and efficiency across the team by establishing best practices for substrate layout, model extraction, and SI/PI validation

Accelerate time-to-market for Synopsys IP by coordinating design phases, technical reviews, and handoffs that keep projects moving without surprises

Influence cross-functional business-unit projects by representing the package design perspective in technical decisions that affect multiple teams

What You'll Need

10+ years of hands-on experience in semiconductor package design, package substrate layout, electrical modeling, or closely related work

Advanced knowledge of circuit theory and transmission line behavior, with the ability to apply it to high-speed package interconnect design and analysis

Demonstrated experience building, validating, and interpreting 3D electromagnetic models using Ansys HFSS or comparable simulation tools

Strong written and verbal communication skills in English, with the ability to explain complex technical tradeoffs to customers, partners, and cross-functional teams

Working knowledge of Windows and Linux environments used for engineering design and analysis workflows

Bachelor's degree in electrical engineering, electronics engineering, or equivalent field

Experience with advanced packaging technologies such as 2.5D interposers, fan-out wafer-level packaging, or chiplet integration is a plus

The Team You'll Be Part Of

You will work with a highly skilled and supportive global team focused on ensuring Synopsys IP test-chip packages meet electrical and physical performance requirements. Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

General Information

Job Title

Sr Staff Package Design Engineer

Job ID

18917

Country

Canada

City

Nepean

State/Province

Nepean

Date Posted

22-Sep-2026

Job Category

Engineering

Job Subcategory

R&D Engineering

Hire Type

Employee

Remote Eligible

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More about this job

Responsibilities

Lead the package design process for advanced IP test chips from requirements definition through final delivery. Coordinate across internal teams and external partners while performing hands-on physical design and electrical modeling to ensure performance requirements are met.

Requirements

Requires 10+ years of experience in semiconductor package design and proficiency with 3D electromagnetic simulation tools like Ansys HFSS. Candidates must hold a bachelor's degree in electrical or electronics engineering and possess strong technical communication skills.

Skills

Package design
Substrate layout
Ansys HFSS
Signal integrity
Power integrity
Electromagnetic modeling
Transmission line theory
Bump maps
Ball maps
Layer stack-up
Semiconductor packaging
2.5D interposers
Chiplet integration
EDA tools
Circuit theory

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

Semiconductor
Package Design
Ansys HFSS
Signal Integrity
Power Integrity
Substrate Layout
Electromagnetic Simulation
Transmission Line
Bump Maps
Ball Maps
Layer Stack-up
2.5D Interposers
Fan-out Wafer-level Packaging
Chiplet Integration
EDA Tools
Circuit Theory
IP Test Chips
Physical Design
Electrical Modeling
Hardware Engineering

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