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Staff Validation/Verification Engineer - 17399
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BERT (Bit Error Rate Tester) and protocol/compliance tools where applicable
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Synopsys

Staff Validation/Verification Engineer - 17399

Ottawa, ON, Canada

Experience: 5+ years of hands-on experience in silicon or hardware validation, with deep focus on DDR and/or LPDDR and/or HBM PHY bring-up and characterization.
Posting language: English
Posted: May 6, 2026

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Original job description

General Information

Job Title

Staff Validation/Verification Engineer - 17399

Job ID

17399

Country

Canada

City

Nepean

State/Province

Nepean

Date Posted

06-May-2026

Job Category

Engineering

Job Subcategory

Validation / Verification Eng

Hire Type

Employee

Remote Eligible

Descriptions & Requirements

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

We are seeking a Staff Validation Engineer to own bring-up, validation, characterization, and debug of high-speed memory PHY subsystems including DDR, LPDDR, and HBM. You will work across silicon, firmware, board, and system domains from first silicon through production readiness and help define validation strategy, lab methodology, and automation infrastructure.

This is a hands-on technical leadership role for someone who is equally comfortable with oscilloscope/VNA/BERT measurements, board-level design tradeoffs, and building automation to scale validation across PVT corners and product generations.

What You'll Be Doing

Lead post-silicon bring-up and validation of DDR, LPDDR, and HBM PHY subsystems on evaluation boards and customer-like platforms.
Execute and own PHY training/tuning validation (read/write leveling, gate training, Vref/ODT, timing alignment, calibration convergence, margining).
Develop and run functional, performance, stress, corner-case, and reliability validation across voltage, temperature, and frequency.
Characterize bandwidth, latency, eye/margin, jitter, BER/error rates, and subsystem stability under real workloads.
Perform hands-on measurements using lab equipment including:
- Real-time and sampling oscilloscopes (eye diagrams, jitter, clock/data analysis)
- Vector Network Analyzer (VNA) for impedance, S-parameters, and channel characterization
- BERT (Bit Error Rate Tester) and protocol/compliance tools where applicable
- Power supplies, logic analyzers, thermal chambers, and related bench equipment
Correlate lab measurements with silicon behavior; drive root-cause analysis from analog/signal-quality observations to firmware/silicon fixes.
Support JEDEC compliance and interoperability testing for DDR/LPDDR families and HBM-related validation flows.
Partner with hardware teams on EVB/validation board design, stack-up, routing, termination, power delivery, and debug access (probes, headers, rework).
Provide feedback on SI/PI, connector/DRAM placement, reference designs, and design-for-validation (DFV) features.
Support board bring-up, BOM review, and hardware rework/debug during validation cycles.
Design and maintain Python/C-based automation for test execution, instrument control, data capture, sweeps, regression, and reporting.
Improve lab efficiency through scripted instrument setups, automated pass/fail criteria, and dashboards for engineering and program reviews.
Influence validation methodology, coverage metrics, and infrastructure for future silicon generations.

The Impact You Will Have

Your validation work directly determines whether Synopsys memory IP is ready to ship, affecting product timelines and customer confidence across the semiconductor industry
The test automation you build scales across multiple IP products and releases, reducing validation cycle time and increasing coverage
Your characterization reports become the technical foundation for customer engagements, sales collateral, and internal design reviews
Debug rigor you bring to silicon issues prevents costly respins and field failures, protecting both schedule and reputation
Test methodologies you develop and standardize become the playbook for future validation engineers joining the Nepean lab
Customer issues you resolve keep high-stakes programs moving, often under tight timelines where your responsiveness is the difference between a delay and a win
The data you collect and analyze feeds back into design improvements, tightening the loop between silicon and specification

What You'll Need

Bachelor's or master's degree in electrical engineering or computer engineering
5+ years of hands-on experience in silicon or hardware validation, with deep focus on DDR and/or LPDDR and/or HBM PHY bring-up and characterization.
Strong understanding of DRAM architecture, memory controller/PHY interaction, JEDEC standards, and training/calibration flows.
Proven experience with board bring-up and practical knowledge of PCB design considerations for high-speed memory (routing, impedance control, power integrity, probing).
Expert-level use of lab equipment: oscilloscopes, VNA, BERT or equivalent high-speed measurement tools; ability to translate measurements into actionable debug.
Strong programming skills in Python and/or C for test automation, instrument control, logging, and data analysis.
Excellent analytical, communication, and cross-functional collaboration skills.
Good to have:

Experience with DDR5, LPDDR5/5X, HBM2e/HBM3 and associated compliance/margining methodologies.
Familiarity with SI/PI simulation (e.g., channel models) and correlation to lab results.
Experience with embedded firmware/BIOS, JTAG/trace, and low-level debug on SoC/ASIC platforms.
Background in AI/accelerator, datacenter, or high-performance SoC memory subsystems.
Experience building validation regression environments and CI-friendly hardware test flows.

Who You Are

You can walk into a lab with a failing test case and walk out two hours later with a root cause and a plan, not just a theory
When data does not make sense, you do not move on, you dig deeper until it does, even if that means questioning the test setup or the spec itself
You are comfortable presenting technical results to design teams, customers, and leadership, translating measurement data into clear conclusions without losing the nuance
You manage multiple validation streams at once, keeping track of what is blocked, what is running, and what needs attention next without dropping threads
You do not wait for perfect documentation or a fully defined test plan, you work with what you have, ask the right questions, and start collecting data
You care about the details, probe placement, grounding, signal integrity, calibration, because you know those details are what separate good data from noise

The Team You'll Be Part Of

You will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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More about this job

Responsibilities

The Staff Validation Engineer will lead the post-silicon bring-up, characterization, and debug of high-speed memory PHY subsystems. They will also develop automation infrastructure and drive root-cause analysis to ensure product readiness and performance stability.

Requirements

Candidates must have a bachelor's or master's degree in electrical or computer engineering and at least 5 years of experience in silicon or hardware validation. Proficiency in lab equipment like oscilloscopes and VNAs, along with strong programming skills in Python or C, is required.

Skills

DDR
LPDDR
HBM
PHY
Python
C
Oscilloscope
VNA
BERT
Signal integrity
Power integrity
PCB design
Silicon validation
JEDEC compliance
Automation
Debug

Benefits

Health benefits
Wellness benefits
Financial benefits

Visa sponsorship

Not detected in the job text

Keywords

Silicon validation
PHY subsystems
DDR
LPDDR
HBM
Python
C
Oscilloscope
VNA
BERT
Signal integrity
Power integrity
PCB design
JEDEC
Automation
Debug
Semiconductor
Firmware
SoC
ASIC
Characterization
Test automation
Hardware validation
Memory controller
Compliance testing
Data analysis
Engineering
Validation methodology
System domains
Product readiness

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